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MT8888CSR Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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Компоненты Описание
производитель
MT8888CSR
ZARLINK
Zarlink Semiconductor Inc ZARLINK
MT8888CSR Datasheet PDF : 25 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MT8888C
Data Sheet
IN+ 1
IN- 2
GS 3
VRef 4
VSS 5
OSC1 6
OSC2 7
TONE 8
WR 9
CS 10
20 VDD
19 St/GT
18 ESt
17 D3
16 D2
15 D1
14 D0
13 IRQ/CP
12 RD
11 RS0
IN+ 1
IN- 2
GS 3
VRef 4
VSS 5
OSC1 6
OSC2 7
NC 8
NC 9
TONE 10
WR 11
CS 12
24 VDD
23 St/GT
22 ESt
21 D3
20 D2
19 D1
18 D0
17 NC
16 NC
15 IRQ/CP
14 RD
13 RS0
NC 5
25 NC
VRef 6
24 NC
VSS 7
23 NC
OSC1 8
22 D3
OSC2 9
21 D2
NC 10
20 D1
NC 11
19 D0
20 PIN PLASTIC DIP/SOIC
24 PIN SSOP
28 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
20 24 28
Name
Description
11
1
22
2
IN+ Non-inverting op-amp input.
IN- Inverting op-amp input.
33
4
GS Gain Select. Gives access to output of front end differential amplifier for
connection of feedback resistor.
44
55
66
6
VRef Reference Voltage output (VDD/2).
7
VSS Ground (0V ).
8 OSC1 DTMF clock/oscillator input. Connect a 4.7 Mresistor to VSS if crystal oscillator is
used.
77
9 OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
8 10 12 TONE Output from internal DTMF transmitter.
9 11 13 WR Write microprocessor input. TTL compatible.
10 12 14
CS Chip Select input. Active Low. This signal must be qualified externally by address
latch enable (ALE) signal, see Figure 14.
11 13 15 RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
12 14 17
RD Read microprocessor input. TTL compatible.
13 15
18 IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this
output goes low when a valid DTMF tone burst has been transmitted or received.
In call progress mode, this pin will output a rectangular signal representative of the
input signal applied at the input op-amp. The input signal must be within the
bandwidth limits of the call progress filter, see Figure 8.
14-17 18-21 19-22 D0-D3 Microprocessor Data Bus. High impedance when CS = 1 or RD = 1.
TTL compatible.
2
Zarlink Semiconductor Inc.

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