M66290AGP Просмотр технического описания (PDF) - Renesas Electronics
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производитель
M66290AGP Datasheet PDF : 54 Pages
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BLOCK DIAGRAM
Xin 14
Xout 13
Vbus 5
T rON 6
Clock
Control
(Oscillator/
PLL)
USB
Peripheral
Circuit
D+ 4
D- 3
USB
Transceiver
TRST 8
TCK 9
T MS 10
TDI 11
TDO 12
TEST1 7
TEST2 41
VCC
1 16 35
Serial
Interface
Engine
Device
Control
Unit
MITSUBISHI <DIGITAL ASSP>
M66290AGP/FP
USB DEVICE CONTROLLER
CPU
Register
17
to A6 to 1
22
23
to D15 to 0
40
45 CS
44 WR
43 RD
4628 INT
Endpoint
Buffer
(3KByte FIFO)
47 Dreq
4688 Dac k
46 RST
2 15 36
GND
BLOCK DESCRIPTIONS
The M66290A contains USB transceiv er, oscillation
circuit, PLL, serial interf ace engine, endpoint buf f er,
dev ice control unit, and CPU register.
USB Transceiv er
USB Transceiv er is consisted of dif f erential driv er
and dif f erential receiv er.
And is compatible with USB specif ication v ersion 1.1
and corresponds to Full Speed Transf er mode.
Serial Interf ace Engine (SIE)
SIE handles protocol lay er as f ollows.
Extract a USB 12MHz clock
Serial-Parallel data conv ersion
SYNC detection
NRZI encode and decode
Bit stuf f ing and destuf f ing
CRC generator and checker
Dev ice Control Unit (DCU)
DCU controls the dev ice state sequence, control
transf er sequence, and so on.
Endpoint Buf f er
This is a FIFO buf f er f or transmit and receiv e
between endpoints.
Except f or EP0 f or control transf er, f iv e endpoints
(EP1 to EP5) can be set.
CPU Register
This is an interf ace block with CPU.
Oscillator/PLL
This block oscillates the internal operation clock
source of 48MHz.
External clock of 6/12/24/48MHz can be input.
USB peripheral circuit
Detect the connection and the shutdown of USB
by the Vbus input.
Connect the Vbus of U SB bus to or the 5V power
supply to Vbus input.
Connect the TrON output to D+ pull-up resistor of
1.5kohm. ON/OFF of the pull-up resistor is controlled
by the register.
2
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