M66256FP Просмотр технического описания (PDF) - Renesas Electronics

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M66256FP

5120 × 8-Bit Line Memory (FIFO)

Renesas Electronics 

M66256FP

5120 × 8-Bit Line Memory (FIFO)

REJ03F0250-0200

Rev.2.00

Sep 14, 2007

Description

The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit

configuration which uses high-performance silicon gate CMOS process technology.

It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between

devices with different data processing throughput.

Features

• Memory configuration:

5120 words × 8 bits (dynamic memory)

• High-speed cycle:

25 ns (Min)

• High-speed access:

18 ns (Max)

• Output hold:

3 ns (Min)

• Fully independent, asynchronous write and read operations

• Variable length delay bit

• Output:

3 states

Application

Digital photocopiers, high-speed facsimile, laser beam printers.

Block Diagram

Data input

D0 to D7

13 14 15 16 21 22 23 24

Data output

Q0 to Q7

1 2 3 4 9 10 11 12

Input buffer

Output buffer

WE 20

Write

enable input

WRES 19

Write

reset input

WCK 17

Write

clock input

VCC 18

Memory array of

5120-word × 8-bit

configuration

5 RE

Read

enable input

6 RRES

Read

reset input

8 RCK

Read

clock input

7 GND

REJ03F0250-0200 Rev.2.00 Sep 14, 2007

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