M66256FP Просмотр технического описания (PDF) - Renesas Electronics

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производитель

M66256FP

5120 × 8-Bit Line Memory (FIFO)

Renesas Electronics 

M66256FP

N-bit Delay 2

(Sliding WRES and RRES at a cycle corresponding to delay length)

WCK

RCK

Cycle 0 Cycle 1 Cycle 2 Cycle n − 2 Cycle n − 1 Cycle n Cycle n + 1 Cycle n + 2 Cycle n + 3

tRESS tRESH

WRES

tRESS tRESH

RRES

tDS tDH

tDS tDH

Dn

(0)

(1)

(2)

(n − 2)

(n − 1)

(n)

(n + 1)

(n + 2)

(n + 3)

m cycles

tAC

tOH

Qn

(0)

(1)

(2)

(3)

WE, RE = "L"

m≥3

N-bit Delay 3

(Disabling RE at a cycle corresponding to delay length)

WCK

RCK

Cycle 0 Cycle 1 Cycle 2

tRESS tRESH

WRES

RRES

RE

tDS tDH

Cycle n − 1 Cycle n Cycle n + 1 Cycle n + 2 Cycle n + 3

tNREH tRES

tDS tDH

Dn

(0)

(1)

(2)

(n − 2)

(n − 1)

(n)

(n + 1)

(n + 2)

(n + 3)

HIGH-Z

Qn

m cycles

tAC

tOH

(0)

(1)

(2)

(3)

WE = "L"

m≥3

REJ03F0250-0200 Rev.2.00 Sep 14, 2007

Page 10 of 13

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