M62230FP Просмотр технического описания (PDF) - Renesas Electronics

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Компоненты Описание

производитель

M62230FP

LCD Matrix Regulator

Renesas Electronics 

M62230FP

Absolute Maximum Ratings

Item

Supply voltage

Maximum output current

Power dissipation

Thermal derating

Operating temperature

Storage temperature

Symbol

VCC

IOUT

Pd

Kθ

Topr

Tstg

Ratings

−36 to 0

30

550

5.5

−20 to +75

−40 to +125

(Ta = 25°C, unless otherwise noted)

Unit

Conditions

V

mA

mW Ta = 25°C

mW/°C Ta > 25°C

°C

°C

Electrical Characteristics

(VCC = −16 V, VIN = GND, VREF = −12 V, Resistor setting = 5R, Ta = 25°C, unless otherwise noted)

Limits

Item

Symbol Min. Typ. Max. Unit

Test Conditions

Supply voltage

VCC

−35



−10

V

Dissipation current

ICC



1.80



mA VREF = −16 V

Output voltage ratio 1

RVO1

1.98 2.00 2.02

 V2 / V1

Output voltage ratio 2

RVO2

1.98 2.00 2.02

 (V5 − V3) / (V5 − V4)

Output voltage ratio 3

RVO3

8.90 9.00 9.10

 V5 / V1

Output voltage ratio 4

RVO4

4.45 4.50 4.55

 V5 / V2

Output voltage ratio 5

RVO5

4.45 4.50 4.55

 V5 / (V5 − V3)

Output voltage ratio 6

RVO6

8.90 9.00 9.10

 V5 / (V5 − V4)

Resistor ratio 1

RR1



4





Resistor between VIN3 and R1 /

resistor between R1 and R2

Resistor ratio 2

RR2



5





Resistor between VIN3 and R2 /

resistor between R1 and R2

Resistor ratio 3

RR3



6





Resistor between VIN3 and R3 /

resistor between R1 and R2

Resistor ratio 4

RR4



7





Resistor between VIN3 and R4 /

resistor between R1 and R2

Resistor ratio 5

RR5



8





Resistor between VIN3 and R5 /

resistor between R1 and R2

Resistor ratio 6

RR6



9





Resistor between VIN3 and R6 /

resistor between R1 and R2

Resistance

R



20



kΩ Resistor between R1 and R2

Load regulation of output voltage 1 ∆V1





20

mV +200 µA < IOUT1 < +10 mA

Load regulation of output voltage 2-1 ∆V2-1





20

mV +200 µA < IOUT2 < +10 mA

Load regulation of output voltage 3-1 ∆V3-1





20

mV +200 µA < IOUT3 < +10 mA

Load regulation of output voltage 2-2 ∆V2-2





20

mV −10 mA < IOUT2 < −200 µA

Load regulation of output voltage 3-2 ∆V3-2





20

mV −10 mA < IOUT3 < −200 µA

Load regulation of output voltage 4 ∆V4





20

mV −20 mA < IOUT4 < −200 µA

Load regulation of output voltage 5 ∆V5





20

mV −20 mA < IOUT5 < −200 µA

Output voltage of regulator

VREG

−1.45 −1.38 −1.31

V Buffer output

Load regulation of VREF

REG-L





50

mV −10 mA < IREG < +2 mA

REJ03D0855-0201 Rev.2.01 Nov 14, 2007

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