M5M5V208AKV Просмотр технического описания (PDF) - Renesas Electronics
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M5M5V208AKV Datasheet PDF : 8 Pages
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RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208AKV series are determined by a
combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with the low
level S1 and the high level S2. The address must be set up before the
write cycle and must be stable during the entire cycle. The data is
latched into a cell on the trailing edge of W,S1 or S2,whichever occurs
first,requiring the set-up and hold time relative to these edge to be
maintained. The output enable input OE directly controls the output
stage. Setting the OE at a high level, the output stage is in a high-
impedance state, and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting W at a high level and OE at a low
level while S1 and S2 are in an active state(S1=L,S2=H).
When setting S1 at a high level or S2 at a low level, the chip are in a
non-selectable mode in which both reading and writing are disabled. In
this mode, the output stage is in a high- impedance state, allowing OR-
tie with other chips and memory expansion by S1 and S2. The power
supply current is reduced as low as the stand-by current which is
specified as ICC3 or ICC4, and the memory data can be held at +2V power
supply, enabling battery back-up operation during power failure or
power-down operation in the non-selected mode.
FUNCTION TABLE
S1 S2
XL
HX
LH
LH
LH
W OE Mode
DQ
X X Non selection High-impedance
X X Non selection High-impedance
LX
HL
HH
Write
Read
Din
Dout
High-impedance
ICC
Stand-by
Stand-by
Active
Active
Active
Note 1: "H" and "L" in this table mean VIH and VIL, respectively.
2: "X" in this table should be "H" or "L".
BLOCK DIAGRAM
A2 18
A3 17
A4 16
A5 15
A6 14
A7 13
A12 12
A14 11
A16 10
A17 9
ADDRESS
INPUTS
A15 7
A13 4
A8 3
A9 2
A11 1
A1 19
A0 20
A10 31
262144 WORDS
X 8 BITS
( 1024 ROWS
X256 COLUMNS
X 8 BLOCKS )
CLOCK
GENERATOR
21 DQ1
22 DQ2
23 DQ3
25 DQ4
26 DQ5
27 DQ6
DATA
INPUTS/
OUTPUTS
28 DQ7
29 DQ8
WRITE
5 W CONTROL
INPUT
30 S1 CHIP
6
S2
SELECT
INPUTS
OUTPUT
32 OE ENABLE
INPUT
8 VCC
24
GND
(0V)
Rev ision-A0.5
2
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