LXT304A Просмотр технического описания (PDF) - Level One
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LXT304A Datasheet PDF : 18 Pages
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bit register. Recovered data is clocked into the ES with the
recovered clock signal, and clocked out of the ES with the
dejittered clock from the JAL. When the bit count in the ES
is within two bits of overflowing or underflowing, the ES
adjusts the output clock by 1/8 of a bit period. The ES pro-
duces an average delay of 16 bits in the receive path.
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The transceiver incorporates a Driver Performance Moni-
tor (DPM) in parallel with TTIP and TRING at the output
transformer. The DPM output goes High upon detection of
63 consecutive zeros. It is reset when a one is detected on
the transmit line, or when a reset command is received.
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The LXT304A transmits data as a 50% AMI line code as
shown in Figure 2. The output driver maintains a constant
low output impedance regardless of whether it is driving
marks or spaces.
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The LXT304A can be controlled through hard-wired pins
(Hardware Mode) or by a microprocessor through a serial
interface (Host Mode). The mode of operation is set by the
MODE pin logic level. The LXT304A can also be com-
manded to operate in one of several diagnostic modes.
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