TMC22071A Просмотр технического описания (PDF) - Fairchild Semiconductor

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TMC22071A

Genlocking Video Digitizer

Fairchild Semiconductor 

PRODUCT SPECIFICATION

TMC22071A

Control and Status Registers

The TMC22071A is controlled by a single 47-bit long Con-

trol Register. Access to the Control Register is via the I/O

Port Shift Register arranged as shown in Figure 1. The Con-

trol Register can be written, with the desired programming.

The 12-bit Status Register is read-only and accessed through

the same l/O Port Shift Register. Reading the Status Register

yields information about blanking level, subcarrier presence,

and whether or not PXCK is locked or unlocked with respect

to the line rate.

Table 1. Microprocessor Port Control

A0 R/W

Action

0

0 Write data from D0 into l/O Port Shift

Register

0

1 Read D0 data from last stage of l/O

Port Shift Register

1

0 Transfer l/O Port Shift Register

contents to Control Register

1

1 Enables continuous update of status

bits in l/O Port Shift Register

D0

I/O Port Shift Register

0

Control Register

46 47 58

Status

Register

65-22071-03

Figure 1. Control and Shift Register Structure

The host processor writes data into the TMC22071A using

only one bit of the microprocessor’s data and address bus. As

shown in Figure 2, the user should bring A0 high for the CS

falling edge preceding the introduction of bit 0 to the D0

port. The next rising edge of CS completes the preloading of

the control data, which transfer into the control register on

the next rising edge of the pixel clock. The I/O Port Shift

Register, Control Register and Status Register are governed

by CS, R/W, and A0. R/W and A0 are latched by the

TMC22071A on the falling edge of CS and data input D0 is

latched on the rising edge of CS. Data read from D0 is

enabled by the falling edge of CS and disabled by the rising

edge of CS. When the Control Register is read more than

once consecutively, an extra CS pulse and accompanying A0

is needed to align the circulated shift register data.

The full sequence of 47 bits of Control Register data must be

written each time a change in that data is desired. All or a

few of the Control and Status Register bits may be read,

but the sequence always begins with bit 58 of the Status

Register.

CS

R/W

D0

A0

46

45

1

0

tH

tS

65-22071-04

Figure 2. Data Write Sequence

CS

R/W

D0

A0

58

57

1

0

Figure 3. Data Read Sequence

65-22071A-05

7

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