TMC22071A Просмотр технического описания (PDF) - Fairchild Semiconductor
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TMC22071A Datasheet PDF : 24 Pages
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TMC22071A
PRODUCT SPECIFICATION
Horizontal Timing
Horizontal line rate is selectable, and is determined by the
FORMAT control bits (12.27 Mpps for NTSC, 13.5 Mpps
for NTSC and PAL). Figure 5 illustrates the horizontal
blanking interval. Figure 6 completes the definition of timing
parameters with vertical blanking interval detail.
Video In
Burst
tDH
GHSYNC
65-22071-07
Figure 5. Horizontal Sync Timing
Video In
H
2.35 µsec PAL
2.3 µsec NTSC
Equalizing Pulse
0.5H
4.7 µsec
Serration
GVSYNC
tVD
GHSYNC
(Odd Field)
tDH
GHSYNC
(Even Field)
Figure 6. Vertical Sync timing
65-22071-08
Programming the TMC22071A
Upon power-up after bringing RESET LOW, the
TMC22071A Control Register is set to default values as
shown in the top entry of Table 3. These default values do
not necessarily render the TMC22071A operational in any
specific application. Before the TMC22071A is expected to
acquire input video, its Control Register must be loaded with
data that is specific to its use.
Table 2.TMC22071A Timing Options
Standard
Field
Rate (Hz)
Line
Rate (kHz)
NTSC
59.94
15.734264
NTSC-601
59.94
15.734264
PAL-601
50.00
15.625
Pixel
Rate (Mpps)
12.2727+
13.50
13.50
PXCK
Frequency (MHz)
24.54+
27.0
27.0
Plxels
Per Line
780
858
864
Table 3. Control Register Example Data
Control Register Data (Bit 56 …… Bit 0)
Standard 46 42 38 34 30 26 22 18 14 10
6
2
DEFAULT 0000 0110 0000 1001 0000 0010 0000 0000 0000 0000 0000 001
NTSC
0010 0110 0000 1001 1000 0010 0000 0000 0000 00xx 0000 000
NTSC-601 0010 0110 0000 1001 1000 0010 0000 0000 0000 00xx 0000 010
PAL-601 0010 1110 0000 1001 1000 0010 0000 0000 0000 00xx 0001 xx0
10
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