LC8953 Просмотр технического описания (PDF) - SANYO -> Panasonic
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Компоненты Описание
производитель
LC8953 Datasheet PDF : 9 Pages
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LC8953
Continued from preceding page.
Number
Name1
120
VDD
121
FC0
122
FC1
123
FC2
124
XBERR
125
XRESET
126
XHALT
127
CPUCLK
128
XDBDIR
129
XBR
130
XBG
131
XBGACK
132
XOWN
133
XEXTDMA1
134
XEXTDMA0
135
XEXTBGAK
136
XCS
137
CLKSEL
138
XSWAP
139
ORGCLK
140
VDD
141
VSS
142
TICKCLK
143
XIACKALL
144
XIACK5
145
XIACK4
146
XIACK3
147
XIACK2
148
XIACK1
149
XIACK0
150
XIRQ5
151
XIRQ4
152
XIRQ3
153
XIRQ2
154
XIRQ1
155
XIRQ0
156
RXD
157
APSEL0
158
APSEL1
159
APSEL2
160
VDD
I/O
Function
–
+5V supply pin
I/O
I/O
MPU function code signal input/output pins
I/O
O
Bus error signal output pin
I
Reset signal input pin
I
Halt signal input pin
O
MPU clock signal output pin
O
Data bus direction signal output pin
O
DMA bus request signal output pin
I
DMA bus request-granted signal input pin
O
DMA bus request-granted acknowledge signal output pin
O
DMA cycle active signal output pin
I/O
DMA signal input/output pins
I/O
I
External DMA bus request-granted acknowledge signal input pin
I
Address decoder mode select signal input pin
I
Master clock (CPUCLK) divider select signal input pin
I
Memory swap function select signal input pin
I
Clock input pin
–
+5V supply pin
–
Ground pin
I
External clock input pin for the tick generator
O
Interrupt acknowledge common signal output pin
O
O
O
Interrupt acknowledge signal output pins
O
O
O
I
I
I
Interrupt request signal input pins
I
I
I
I
Mouse data signal input pin
O
O
General-purpose output port pins
O
–
+5V supply pin
1. An “X” at the beginning of a pin name indicates negative logic.
No.3411–6/9
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