KL5KUSB201 Просмотр технического описания (PDF) - Unspecified

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KL5KUSB201

USB2.0 Compliant Transceiver Chip Datasheet (Digest)

Unspecified 

Kawasaki USB device

KL5KUSB201

Datasheet (digest) rev 1.1E page 7/21

internal 12MHz clock instead of FrontEnd, HSDLL and EBUF blocks. For received

signals, the LSI locks them in HS DLL and is buffering them in EBUF. Then signals

are transferred to Shared Logic to convert data format, check the CRC, convert from

serial to parallel. The data is finally delivered to the SIE bus through SIE_IF. For

transmit operation, incoming parallel data is received in SIE_IF and sent to Shared

Logic to perform parallel to serial conversion, CRC generation, bit stuffing and NRZI

encoding. Finally the data is transmitted onto the USB bus through FrontEnd block.

High Speed or Full Speed operation is selected by SIE control signals. USB bus status

can be monitored by USB bus status signals.

Figure 2 KL5KUSB201 Internal Architecture

USB bus

HSDP

HSDM

HS

FrontEnd

RPU_ENA

FSDP

FSDM

FS

FrontEnd

HS

DLL

EBUF

DPLL

Shared

Logic

SIE bus

CTRL

STATUS

SIE_IF CKOUT

SIE_DAT

External

48MHz clock

CLK

GEN

Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

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