KL5KUSB201 Просмотр технического описания (PDF) - Unspecified
Номер в каталоге
Компоненты Описание
производитель
KL5KUSB201 Datasheet PDF : 21 Pages
| |||
Kawasaki USB device
KL5KUSB201
Datasheet (digest) rev 1.1E page 6/21
generation (optional), bit stuffed and NRZI encoded. Packet is transmitted onto
USB bus with SYNC and EOP attached
5. USB Bus status is delivered for outside SIE to monitor it
6. Function is controlled by Input Signals
7. Function defined by UTMI Specification is supported
8. Stand-alone Test packet generation for High Speed Signal Quality
1.2 KL5KUSB201 Product Feature
KL5KUSB201 Product Feature is shown below.
Table 1-2 KL5KUSB201 Product Feature
No Item
Feature
1 Process
0.18um CMOS
2 Package
LQFP 80 pin plastic package
3 Input Clock Frequency
48MHz
4 Internal Clock Frequency
480MHz、48MHz and other
5 Output Clock Frequency
30MHz
(CKOUT)
6 USB port
1 port
(USB pin is separated for HS and FS)
7 Parallel Data width (SIE_DAT) 16bit
8 Power voltage
3.3±0.3V、1.8±0.15V
9 Operation Current in FS
typical 50mA
10 Operation Current in HS
typical 90mA
11 Operation Current at suspend 1uA
12 Ambient Temperature
0～70°C
Please contact to our sales and marketing person to request samples, datasheet,
USB201 IP and / or HS_SIE included ASCP planning.
2. Chip Architecture
Internal Architecture of KL5KUSB201 is shown in figure 2. The LSI consists of 6 major
blocks as follows. FrontEnd block transmits and receives USB signals. HS DLL
block is used to re-clock High Speed signals with internal 480MHz clock. EBUF block
is for buffering High Speed signals. Shared Logic block includes such function as
NRZI decode, bit un-stuffing, CRC check, serial to parallel conversion for both High
Speed and Full Speed USB signals. SIE_IF block interfaces with SIE bus signals. For
Full Speed operation, DPLL block is used to re-clock the Full Speed signals with
Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.
Share Link: 