KL5KUSB201 Просмотр технического описания (PDF) - Unspecified

Номер в каталоге

Компоненты Описание

производитель

KL5KUSB201

USB2.0 Compliant Transceiver Chip Datasheet (Digest)

Unspecified 

Kawasaki USB device

KL5KUSB201

Datasheet (digest) rev 1.1E page 5/21

1. Overview

Kawasaki Microelectronics Inc. and Kawasaki LSI Inc. introduce KL5KUSB201 LSI,

which is designed based on USB Specification revision 2.0 and operates as both

USB2.0 High Speed and Full Speed transceiver chip. It has two modes – UTMI

Specification compatible mode and Kawasaki Original mode. In Kawasaki Original

mode, the LSI has several convenient function such as automatic CRC generation and

verification, transmit packet abortion and automatic test packet generation for High

Speed Signal Quality test. The LSI is recognized as USB2.0 PHY chip and customers

are able to build up USB2.0 compliant device system with their logic and PHY control /

endpoint buffer function (SIE), which is available by Kawasaki or other IP vendor.

Figure 1. KL5KUSB201 Image

1.1 Chip Functionality

KL5KUSB201 Fucntionality is summarized below.

1. HS Chirp Signal Generation and Detection

2. Support for both High Speed (480Mbit/sec) and Full Speed (12Mbit/sec)

3. For received packet, phase lock, buffering, SYNC detection, NRZI decode, bit

un-stuffing, CRC error detection (optional), serial to parallel conversion are

performed. 16bit data is drived on SIE bus

4.For packet transmission, parallel 16bit data is received, serialized, CRC

Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

Share Link: