LZ9GF16 Просмотр технического описания (PDF) - Sharp Electronics
Номер в каталоге
Компоненты Описание
производитель
LZ9GF16 Datasheet PDF : 22 Pages
| |||
SHARP
LZ9GF16
4
1
4. Explanation of Input / Output signal
.
?IN No.’ Signal Name
Explanation
I/O
1I
VIN
Vertical sync. Signal input (Positive)
I
2
CVOP Vertical sync. Signal Output for Count Downcircuit
0
3
CVIN Vertical sync. Signal input for Count Downcircuit
I
4
DVOP Vertical sync. Signal output for digital separator circuit (Positive)
0
5
FBJT Polarity alternating signal output for commonelectrode driving signal
0
6
GPS Logic pals output for gate driver power supply making
0
7
GND Ground
a
EXCL Input / Output for outside Clock signal
I/O
9
SYNI Composite sync. signal input
I
10
HSY Internal horizontal sync. signal output (Negative)
I/O
11
VSY Internal vertical sync. signal output (Negative)
I/O
12
DIS
Control signal output for source driver
0
13
TEST0 Monitor signal output for test
0
14
NTPC Terminal for display mode change NTSCor PAL [Note11
I
15
VRVC Input for the Vertical scanning direction setting (Note21
I
16
HRVC Input for the horizontal scanning direction setting (Note31
I
17
CHK Output for signal of backlight brightness control
0
ia
TEST1 Input terminal for test (Note41
I
19
TEST0 Monitor signal output for test
0
20
IVB
Scanning s_e-tt-ing input for gate driver
0
21
SPS Besetting signal output for gate driver
0
22
CLS Clock sign._a_l . output for gate driver
0
23
LOW0 Control signal output for gate driver
0
24
CT& Control--_s_ignal _o_u_tp_u_t- for source driver
0
25
SPD Starting signal output for source driver
26
CLD Clock__s--ig_n- al ou_t.p-ut for source driver
27
osco
Output _-f-o-r_ cloc.-k-- oscillator circuit
/0
28 , oscI ..I_n_p_ut- for -c-l.o_c-k..._o--s.c-il_la_t_o-r circuit
-____
/ _I.-
29 I SAM0 ~----Ct--o-n--tr-o--l-.~s..ig. nal --.o.utp~u_t_ for source driver
30 j
bD
IPow_er s._up..p-.ly-~-v-o-ltag-.e.__--__
~-______
31 / GND fIG---ro--u-n--d;. _- ---- --
-
-__
3-_2 _
---3_3_
7I ---./-I-nFp-Tu~LEt~O-S-f;-W;~T--i1n1‘-i-.-..- IInput terminal fil foryet;;e7s-;tj(-Ngao1te41
~~~--~
-__-
1-- -L--I -.--
.__34
35 I
IPoIarlty alternating<ign-.&-%-$ut
for video signa
RESH TGi%t!l-counter
resetting input (Note51
-__ --i--t-
-~-3-6- :
PDP IOutput for_phasecom-p-a.-r-ative signal of PLL circuit
-------------,~ 1 o--
__3_7__._’___~ RESV /Vertica_l_ ._~c~o.u..n..t.e_r~. r.-es_e_tting ..-i.nput (Note61
38
_--3-9 ;
TEST1
TEST1
-I-
Input __te-r..m_inal
IInpu_t __t.er-m_-ina.l-.
for. te~s.-t--- (Note41
for --t.e-_s_t -__ (Note41
~-____-__
____---
-_.~
--j--‘-t
.-.4-0 ~~F--- A&y-:--. iHorizontal- -.-s.canning setting output for source dr_iv-_e_r --~-~
--
_-4.-1-----e-.---.
,Horlzontal--- scanning setting outp-u_t_--f_o_r_ source driver
___-
42 ~ CLOC Input for EXCLsi&l-outpu%etting
(Note71____
VSYsignal input / output setting (Note81
Share Link: 