PM4354 Просмотр технического описания (PDF) - PMC-Sierra
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PM4354 Datasheet PDF : 463 Pages
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PM4354 COMET-QUAD
DATASHEET
PMC-1990315
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ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
12.13.6 RECEIVE CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE
SETTINGS .......................................................................................... 391
12.13.7 TRANSMIT CLOCK MASTER: FULL T1/E1 MODE SETTINGS ........ 392
12.13.8 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE SETTINGS ....... 393
12.13.9 TRANSMIT CLOCK MASTER: CLEAR CHANNEL MODE SETTINGS393
12.13.10 TRANSMIT CLOCK SLAVE: FULL T1/E1 MODE SETTINGS.......... 394
12.13.11 TRANSMIT CLOCK SLAVE: CLEAR CHANNEL MODE SETTINGS394
12.13.12 TRANSMIT CLOCK SLAVE: H-MVIP MODE SETTINGS................. 395
12.13.13 TRANSMIT CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE
SETTINGS .......................................................................................... 397
12.14 H-MVIP DATA FORMAT ................................................................................... 398
12.15 JTAG SUPPORT .............................................................................................. 401
12.15.1 TAP CONTROLLER ............................................................................ 403
FUNCTIONAL TIMING .................................................................................................. 410
13.1 BACKPLANE RECEIVE SERIAL CLOCK AND DATA INTERFACE TIMING ... 410
13.2 BACKPLANE RECEIVE H-MVIP TIMING ........................................................ 415
13.3 BACKPLANE TRANSMIT SERIAL CLOCK AND DATA INTERFACE TIMING 416
13.4 BACKPLANE TRANSMIT H-MVIP TIMING ..................................................... 424
ABSOLUTE MAXIMUM RATINGS ................................................................................ 426
D.C. CHARACTERISTICS ............................................................................................ 427
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS.............................. 429
COMET-QUAD TIMING CHARACTERISTICS ............................................................. 433
17.1 RSTB TIMING .................................................................................................. 433
17.2 XCLK INPUT TIMING....................................................................................... 433
17.3 TRANSMIT BACKPLANE INTERFACE (FIGURE 83, FIGURE 84)................. 434
17.4 RECEIVE BACKPLANE INTERFACE (FIGURE 85, FIGURE 86) ................... 437
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
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