F25L32PA-100PAG Просмотр технического описания (PDF) - [Elite Semiconductor Memory Technology Inc.

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производитель

F25L32PA-100PAG

3V Only 32 Mbit SerialFlash Memory with Dual

[Elite Semiconductor Memory Technology Inc. 

ESMT

F25L32PA

„ PIN DESCRIPTION

Symbol

SCK

SI / SIO0

SO / SIO1

CE

WP

HOLD

VDD

VSS

Pin Name

Serial Clock

Serial Data Input /

Serial Data Input Output 0

Serial Data Output /

Serial Data Input Output 1

Chip Enable

Write Protect

Hold

Power Supply

Ground

Functions

To provide the timing for serial input and output operations

To transfer commands, addresses or data serially into the device. Data is

latched on the rising edge of SCK (for Standard mode). / Bidirectional IO pin to

transfer commands, addresses or data serially into the device on the rising

edge of SCK and read data or status from the device on the falling edge of

SCK(for Dual mode).

To transfer data serially out of the device. Data is shifted out on the falling edge

of SCK (for Standard mode). / Bidirectional IO pin to transfer commands,

addresses or data serially into the device on the rising edge of SCK and read

data or status from the device on the falling edge of SCK (for Dual mode).

To activate the device when CE is low.

The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status

register.

To temporality stop serial communication with SPI flash memory without

resetting the device.

To provide power.

„ FUNCTIONAL BLOCK DIAGRAM

Page Address

Latch / Counter

High Voltage

Generator

Status

Register

Byte Address

Latch / Counter

Memory

Array

Page Buffer

Y-Decoder

Command and Conrol Logic

Serial Interface

CE SCK SI

SO WP HOLD

(SIO0) (SIO1)

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 1.0

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