PSD834F2-10J Просмотр технического описания (PDF) - STMicroelectronics

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PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Complex PLD (CPLD)

The CPLD can be used to implement system logic

functions, such as loadable counters and shift reg-

isters, system mailboxes, handshaking protocols,

state machines, and random logic. The CPLD can

also be used to generate three External Chip Se-

lect (ECS0-ECS2), routed to Port D.

Although External Chip Select (ECS0-ECS2) can

be produced by any Output Macrocell (OMC),

these three External Chip Select (ECS0-ECS2) on

Port D do not consume any Output Macrocells

(OMC).

As shown in Figure 10, the CPLD has the following

blocks:

■ 24 Input Macrocells (IMC)

■ 16 Output Macrocells (OMC)

■ Macrocell Allocator

■ Product Term Allocator

■ AND Array capable of generating up to 137

product terms

■ Four I/O Ports.

Each of the blocks are described in the sections

that follow.

The Input Macrocells (IMC) and Output Macrocells

(OMC) are connected to the PSD internal data bus

and can be directly accessed by the MCU. This

enables the MCU software to load data into the

Output Macrocells (OMC) or read data from both

the Input and Output Macrocells (IMC and OMC).

This feature allows efficient implementation of sys-

tem logic and eliminates the need to connect the

data bus to the AND Array as required in most

standard PLD macrocell architectures.

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