PSD834F2V
Figure 10. PLD Diagram
8
ATA
PAGE
US
REGISTER
DECODE PLD
8
73
4
1
1
2
1
PRIMARY FLASH MEMORY SELECTS
SECONDARY NON-VOLATILE MEMORY SELECTS
SRAM SELECT
CSIOP SELECT
PERIPHERAL SELECTS
JTAG SELECT
16 OUTPUT MACROCELL FEEDBACK
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
t(s) CPLD
16 OUTPUT
c MACROCELL
MACROCELL
u PT
ALLOC.
d 73
ALLOC.
ro 24 INPUT MACROCELL
(PORT A,B,C)
lete P DIRECT MACROCELL INPUT TO MCU DATA BUS
bso 24
INPUT MACROCELL & INPUT PORTS
MCELLAB
TO PORT A OR B 8
MCELLBC
TO PORT B OR C 8
3
EXTERNAL CHIP SELECTS
TO PORT D
Obsolete Product(s) - O 3
PORT D INPUTS
AI02872
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