UPSD3212 Просмотр технического описания (PDF) - STMicroelectronics

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UPSD3212

Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

STMicroelectronics 

UPSD3212C, UPSD3212CV

Table 117. ISC Timing (3V Devices)

Symbol

Parameter

tISCCF Clock (TCK, PC1) Frequency (except for PLD)

tISCCH Clock (TCK, PC1) High Time (except for PLD)

tISCCL Clock (TCK, PC1) Low Time (except for PLD)

tISCCFP Clock (TCK, PC1) Frequency (PLD only)

tISCCHP Clock (TCK, PC1) High Time (PLD only)

tISCCLP Clock (TCK, PC1) Low Time (PLD only)

tISCPSU

tISCPH

tISCPCO

ISC Port Set Up Time

ISC Port Hold Up Time

ISC Port Clock to Output

tISCPZV ISC Port High-Impedance to Valid Output

tISCPVZ ISC Port Valid Output to High-Impedance

Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.

2. For Program or Erase PLD only.

Conditions

Min

(Note 1)

(Note 1)

40

(Note 1)

40

(Note 2)

(Note 2)

240

(Note 2)

240

12

5

Figure 77. MCU Module AC Measurement I/O Waveform

Max

Unit

12

MHz

ns

ns

2

MHz

ns

ns

ns

ns

30

ns

30

ns

30

ns

VCC – 0.5V

0.45V

0.2 VCC + 0.9V

Test Points

0.2 VCC – 0.1V

AI06650

Note: AC inputs during testing are driven at VCC–0.5V for a logic '1,' and 0.45V for a logic '0.'

Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0'

Figure 78. PSD MODULE AC Float I/O Waveform

VLOAD + 0.1V

VLOAD – 0.1V

0.2 VCC – 0.1V

Test Reference Points

VOH – 0.1V

VOL + 0.1V

AI06651

Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to

float when a 100mV change from the loaded VOH or VOL level occurs

IOL and IOH ≥ 20mA

144/152

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