UPSD3212 Просмотр технического описания (PDF) - STMicroelectronics

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UPSD3212

Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM

STMicroelectronics 

UPSD3212C, UPSD3212CV

Figure 75. Reset (RESET) Timing

VCC

RESET

VCC(min)

tNLNH-PO

Power-On Reset

tOPR

tNLNH

Warm Reset

tOPR

AI07437

Table 112. Reset (RESET) Timing (5V Devices)

Symbol

Parameter

Conditions

tNLNH

RESET Active Low Time(1)

tNLNH–PO

Power-on Reset Active Low Time

tOPR

RESET High to Operational Device

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

Table 113. Reset (RESET) Timing (3V Devices)

Symbol

Parameter

Conditions

tNLNH

RESET Active Low Time(1)

tNLNH–PO

Power-on Reset Active Low Time

tOPR

RESET High to Operational Device

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

Table 114. VSTBYON Definitions Timing (5V Devices)

Symbol

Parameter

Conditions

tBVBH

VSTBY Detection to VSTBYON Output High

(Note 1)

tBXBL

VSTBY Off Detection to VSTBYON Output

Low

(Note 1)

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.

Table 115. VSTBYON Timing (3V Devices)

Symbol

Parameter

tBVBH

VSTBY Detection to VSTBYON Output High

tBXBL

VSTBY Off Detection to VSTBYON Output

Low

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.

Conditions

(Note 1)

(Note 1)

Min

Max

Unit

150

ns

1

ms

120

ns

Min

Max

Unit

300

ns

1

ms

300

ns

Min

Typ

Max Unit

20

µs

20

µs

Min

Typ

Max Unit

20

µs

20

µs

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