MBM29SL160BD Просмотр технического описания (PDF) - Fujitsu

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MBM29SL160BD

FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT

Fujitsu 

MBM29SL160TD-10/-12/MBM29SL160BD-10/-12

The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit),

or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 13,

Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by

the system at this particular instance of time. Hence, Data Polling must be performed at the memory location

which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during the

programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

Figure 21 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the devices will automatically program and verify the entire memory for an all

zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or

RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command

sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the

device returns to read the mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

Figure 22 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever

happens later, while the command (Data = 30H) is latched on the rising edge of CE or WE which happens first.

After time-out of 50µs from the rising edge of the last sector erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 7. This sequence

is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently

erased. The time between writes must be less than 50µs otherwise that command will not be accepted and

erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this

condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50µs

from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase

command(s). If another falling edge of CE or WE, whichever happens first occurs within the 50µs time-out window

the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3,

Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will

reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution

has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to

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