DS28E04-100 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS28E04-100

4096-Bit Addressable 1-Wire EEPROM with PIO

Dallas Semiconductor -> Maxim Integrated 

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of the

DS28E04-100. The DS28E04-100 has five main data components: 1) 64-bit device ID number, 2) 32-byte

scratchpad, 3) sixteen 32-byte pages of EEPROM, 4) Special Function Register, and 5) PIO Control Registers. The

hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the eight

ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional Search ROM, 5) Skip

ROM, 6) Resume, 7) Overdrive-Skip ROM or 8) Overdrive-Match ROM. Upon completion of an Overdrive ROM

command byte executed at standard speed, the device enters Overdrive mode where all subsequent

communication occurs at a higher speed. The protocol required for these ROM function commands is described in

Figure 14. After a ROM function command is successfully executed, the memory/control functions become

accessible and the master may provide any one of the nine Memory/Control Function commands. The protocol for

these commands is described in Figure 9. All data is read and written least significant bit first.

Figure 1. Block Diagram

Internal VDD

VCC

1-Wire Network

IO

1-Wire

Function Control

P0

P1

POL

Memory

Function

Control Unit

PIO

Control Registers

Device ID

Number Register

A0

A6

CRC16

Generator

Data Memory

16 Pages of

32 Bytes Each

Special Function

Registers

32-Byte

Scratchpad

Internal VDD

5 of 36

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