HDMP-1546 Просмотр технического описания (PDF) - HP => Agilent Technologies

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HDMP-1546

Fibre Channel Transceiver Chip

HP => Agilent Technologies 

alternately used to clock the 10-

bit parallel output data.

An optional -LCKREF pin is

available for users who want to

gain full control during the

frequency acquisition process.

Asserting this pin will force the

Rx PLL to fully phase and

frequency lock onto the reference

clock, disregarding the serial

stream completely.

To enable the auto-locking

feature, the -LCKREF pin should

be tied to VCC. The receiver will

detect the absence of high-speed

serial data into +DIN (pin 54)

and -DIN (pin 52) and lock onto

the reference clock (REFCLK).

RBC0 and RBC1 will remain

frequency locked to 53.125 MHz.

The receiver will frequency and

phase lock onto the incoming

valid data once it is reapplied.

INPUT SAMPLER

The INPUT SAMPLER is

responsible for converting the

serial input signal into a re-timed

serial bit stream. In order to

accomplish this, it uses the high

speed serial clock recovered from

the RX PLL/CLOCK RECOVERY

block. This serial bit stream is

sent to the FRAME DEMUX and

BYTE SYNC block.

FRAME DEMUX AND BYTE

SYNC

The FRAME DEMUX AND BYTE

SYNC block is responsible for

restoring the 10-bit parallel data

from the high speed serial bit

stream. This block is also

responsible for recognizing the

comma character (or a K28.5

character) of positive disparity

(0011111xxx). When recognized,

the FRAME DEMUX AND BYTE

SYNC block works with the RX

PLL/CLOCK RECOVERY block to

properly align the receive byte

clocks to the parallel data. When

a comma character is detected

and realignment of the receiver

byte clocks (RBC1/RBC0) is

necessary, these clocks are

stretched, not slivered, to the

next possible correct alignment

position. These clocks will be

fully aligned by the start of the

second 4-byte ordered set. The

second comma character received

shall be aligned with the rising

edge of RBC1. Comma characters

should not be transmitted in

consecutive bytes to allow the

receiver byte clocks to maintain

their proper recovered

frequencies.

OUTPUT DRIVERS

The OUTPUT DRIVERS present

the 10-bit parallel recovered data

byte properly aligned to the

receiver byte clocks

(RBC1/RBC0), as shown in

Figure 5. These output data

buffers provide TTL compatible

signals.

Recommended Handling

Precautions

Additional circuitry is built into

the various input and output pins

on this chip to protect against

low level electrostatic discharge;

however, they are still ESD

sensitive. Standard procedures

for static sensitive devices should

be used in the handling and

assembly of this product.

699

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