TQ9303 Просмотр технического описания (PDF) - TriQuint Semiconductor
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TQ9303 Datasheet PDF : 25 Pages
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TQ9303
Proprietary Link Mode (continued)
When PL_IDLE is driven low, data words on CTXD0..31
are encoded just as in Fibre Channel operation. When
PL_IDLE is driven high, the TQ9303 encodes one EOFa
ordered set followed by IDLE ordered sets for as long
as PL_IDLE remains high.
generation, the CRXS1 signal is used to indicate CRC
errors. When not using the CRC, CRXS1 should be
ignored. For non-Fibre Channel designs making use of
the PL_IDLE input, the CRXSO output can be used to
distinguish received data from idle time.
Decoder Section
The EOFa ordered set is used to ensure proper running
disparity. When using the PL_IDLE signal, IDLE
ordered sets do not force proper running disparity. It is
therefore necessary to transmit at least one word with
PL_IDLE low followed by at least one word with
PL_IDLE high in order to guarantee proper running
disparity.
Without proper running disparity, the receiver portion
of the TQ9303 may flag the IDLE ordered sets as
errors and prevent the word sync state machine from
reaching the synchronized state as long as the running
disparity is incorrect.
Without proper running disparity, the receiver portion
of the TQ9303 may flag the IDLE ordered sets as errors
and prevent the word sync state machine from
reaching the synchronized state as long as the running
disparity is incorrect.
The contents and parity of CTXD0..31 and CTXP0..3 are
ignored during the word cycles when PL_IDLE is held
high. If CTXC1 is low, then CRC checking will occur,
which may cause the TXCERR signal to indicate an
error, which can be ignored in proprietary designs. If
CTXC1 is driven high, then the TQ9303 will generate a
32-bit CRC word during the first word cycle of PL_IDLE
high. During the second word cycle of PL_IDLE high,
the EOFa will be encoded followed by IDLE ordered
sets. Therefore, at least two word cycles of PL_IDLE
high between data bursts must be provided when using
CRC generation (that is, CTXC1␣ high). When using CRC
The Decoder has several functional blocks:
10b/8b Decoder, Ordered Set Decoder, Word Sync
Detector, Line State Decoder, 32-bit CRC Checker,
Parity Generator, and Clock Generator.
The Decoder section has two modes of operation: the
Normal mode and Raw mode. In the Normal mode, the
Decoder section takes 10 bits of data from the Receiver
output, decodes it using 10b/8b, decodes ordered sets,
checks CRC, combines four bytes into a single word
output, and generates parity. In the Raw mode, the
Decoder section directly combines the bytes into
words, bypassing 10b/8b decoding, ordered set
decoding, CRC checking, and parity generation.
The following is the decode sequence data flow:
1. Byte Input
2. Byte–to–Half-Word Conversion
3. 10b/8b Decoding
4. Ordered Set Decoding
5. Line State Decoding
6. Word Sync Generation
7. 32-Bit CRC Checking
8. Muxing between Ordered Set, Unchanged Input,
10b/8b Decoded Input, and Status Bits
9. Half-Word–to–Word Conversion
10. Parity Generation
11. Word Output
8
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