TQ9303 Просмотр технического описания (PDF) - TriQuint Semiconductor

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TQ9303

Fibre Channel Encoder/Decoder

TriQuint Semiconductor 

TQ9303

(which does not correspond to any predefined Fibre

Channel ordered set) the ENDEC will send the user the

same value, 8500FF00h, while holding CRXS0 high. It

is up the the user to examine the second, third, and

fourth bytes of “special” ordered sets to identify them.

8b/10b Encoder Block

The 8b/10b Encoder encodes 8-bit-wide data to 10-bit-

wide data to improve its transmission characteristics.

The 8b/10b coding scheme maintains the signal DC

balance by keeping the same number of ones and zeros

for easier receiver designs, provides good transition

density for improved clock recovery, and improves

error checking. It also forces the correct running

disparity when encoding line states, idles, or receiver-

ready ordered sets. Appendix A contains the lookup

tables for the 8b/10b coding scheme.

Clock Generator Block

The Clock Generator generates word, half-word, and

byte clocks required by other blocks in the Encoder. It

uses BTXCKIN (a byte clock) from the transmitter as a

reference clock. For example, using Fibre Channel data

rates, BTXCKIN runs at 106.25␣ MHz using FC1063,

53.125␣ MHz using FC531, and 26.5625␣ MHz using

FC266. The Clock Generator generates BTXCKOUT for

clocking BTXD0..9. It also generates CTXWREF, a word

clock used by the host to generate CTXCLK, which

clocks the host I/O registers. CTXCLK runs at

25.5625␣ MHz using FC1063, 13.28125␣ MHz using

FC531, and 6.640625␣ MHz using FC266.

Raw Mode Transmit

In Raw Mode Transmit where TXRAW is high for the

whole frame, the input data word bypasses the parity

check, ordered set generator, CRC, and 8b/10b, and is

directly converted to bytes of data. The word-to-byte

mapping of input to output is listed in Table␣ 1. Note that

in raw mode, a “raw” word may be inserted into the

data flow at any time, although running disparity will be

forced negative and the word sync detector state

machine will reset.

Proprietary Link Mode

The PL_IDLE (Proprietary Link IDLE) input can be used

to simplify designs that do not have to conform to Fibre

Channel standards. In such designs the CTXC0 input is

driven low (that is, grounded) and the PL_IDLE pin is

used to distinguish data from nondata. The PL_IDLE

pin controls a bit logic in front of the input registers of

the CTXC0 and CTXD24..31 inputs. It was added to

make it easier for users who aren’t concerned with the

Fibre Channel protocol, but simply want to control the

transmission of data without habing to mux control

information into their data paths in order to control the

CTXD24..31 pins for ordered set control.

On the rising edge of CTXCLK on the first cycle of

PL_IDLE going high, the input registers for CTXC0 and

CTXD24..31 are “jammed” with the value that would

make the ENDEC encode an EOFa. As long as PL_IDLE

is held high, these input registers are jammed with the

value that would make the ENDEC encode an IDLE

ordered set. If CTXC1 is low (check mode) CTXERR will

properly reflect the validity of CRC contained in the

user’s data (assuming the user’s data contains CRC), or

it can be ignored if no CRC is used. If CTXC1 is high

(generate mode), the ENDEC will insert CRC before

encoding the EOFa followed by IDLEs. This creates a

situation in which the user’s data will begin as soon as

PL_IDLE is dropped (with no preceding SOF); but it

does not present a problem for the ENDEC, because the

CRC blocks in both Rx and Tx halves are initialized by

any ordered set. Thus, the IDLE ordered set that

preceeds the user’s data is sufficient to ensure proper

CRC calculation.

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For additional information and latest specifications, see our website: www.triquint.com

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