TQ9303 Просмотр технического описания (PDF) - TriQuint Semiconductor

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TQ9303

Fibre Channel Encoder/Decoder

TriQuint Semiconductor 

TQ9303

CTXPERR (Transmit Parity ERRor) is driven high

when an error is detected in the parity check mode.

When parity checking is disabled, CTXPERR is driven

low. In Raw Mode transmit, where the data flow

bypasses the parity check, 32-bit CRC, 8b/10b encoder,

and ordered set encoder, CTXPERR is driven low.

32-Bit CRC Block

32-bit Cyclic Redundancy Checking (CRC) generates

or checks CRC, depending on CTXC1. CTXC1 high

generates CRC, while CTXC1 low checks CRC for the

incoming frame. The CRC used in Fibre Channel is the

same as FDDI's frame check sequence, where a 32-

bit CRC is computed for every frame, starting after

SOF (Start Of Frame) and ending a byte before EOF

(End Of Frame). The resulting 32-bit CRC is

automatically inserted into the frame before EOF.

In the check CRC mode, CTXCERR (Transmit Crc

ERRor) is driven high when a CRC error is detected.

In the generate CRC mode, CTXCERR is driven low. In

Raw Mode transmit where the data flow bypasses the

parity check, 32-bit CRC, 8b/10b encoder, and ordered

set encoder, CTXCERR is driven low.

The Generate CRC mode timing diagrams are shown in

Figure 3. CTXC1 is high for the entire frame, when

generating CRC. CTXC0 is high only for the duration of

SOF, indicating that the input word (CTXD0..31) is an

ordered set. Similarly, CTXC0 is high for the duration of

EOF, which is another ordered set. The 32-bit CRC

block computes the CRC for data after SOF and before

EOF. The resulting CRC is inserted between the last

data word and EOF at the output (BTXD0..9).

The Check CRC mode timing diagrams are shown in

Figure 4. CTXC1 is low for the whole frame when

checking CRC. CTXC0 is high only for the duration of

SOF, indicating that the input word (CTXD0..31) is an

ordered set. Similarly, CTXC0 is high for the duration of

EOF, another ordered set. 32-bit CRC begins after SOF

Figure 3. Generate CRC Mode TIming

CRC Computation

CTXD0..31

SOF

D0

D1

Dn

EOF

"d"

Idle

CTXC1

CTXC0

BTXD0..9

4 Bytes

SOF

D0

Dn-1

Dn

CRC

EOF

4

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