TQ9303 Просмотр технического описания (PDF) - TriQuint Semiconductor
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TQ9303 Datasheet PDF : 25 Pages
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TQ9303
Functional Description
The TQ9303 may be divided into two independent
functional sections: the Encoder and Decoder, as
shown in Figure 2. The Encoder section describes the
flow of data from the host to the transmitter.
Conversely, the Decoder section describes the flow of
data from the receiver to the host. Designed for full-
duplex operation, the Encoder and Decoder will
transmit and receive one at a time or simultaneously.
The Encoder performs 8b/10b encoding of information
from the host to the transmitter. The Decoder performs
10b/8b decoding of information from the receiver to
the host. The host interface is denoted by a letter C (as
in CTXP), and the transmit/receive interface is denoted
by a letter B (as in BTXD0). Pins within the Encoder
section are denoted with the letters TX (as in CTXP),
and pins within the Decoder section are denoted with
RX (as in CRXS1). At the host interface, the TQ9303
has a 32-bit transmit data bus and a 32-bit receive data
bus, each with 4-bit parity and 8-bit control. The
transmitter and receiver interfaces to the TQ9303 are
10-bit data buses. Table␣ 5 includes all the pin
descriptions. Detailed descriptions of the Encoder and
Decoder sections follow.
Encoder Section
The Encoder has several functional blocks:
Parity Check, 32-Bit CRC, Ordered Set generator,
8b/10b Encoder, and Clock Generator. The Encoder
section has two modes of operation: Normal mode and
Raw mode. In the Normal mode, the Encoder section
receives a word from the host interface, checks parity,
calculates CRC, divides the word into bytes, encodes
them using 8b/10b, and generates a 10-bit output, as
illustrated in Figure 2. In the Raw mode, the Encoder
section receives a word from the host interface without
parity check, CRC check, or 8b/10b encoding.
The following is the encode sequence data flow:
1. Word input
2. Parity check
3. Word–to–half-word conversion
4. Ordered set encoding
5. 32-bit CRC check or generate
6. Muxing between ordered set, 32-bit CRC, and
unchanged input
7. 8b/10b encoding
8. Muxing between unchanged input and
encoded word
9. Half-word–to–byte conversion
10. Byte output
Parity Check Block
Parity check depends on the TXPENN (Transmit Parity
ENable Not) input. TXPENN high ignores parity, while
TXPENN low checks parity for each byte on the data
bus, CTXD0..31. There are four parity bits (CTXP0..3),
each bit corresponding to a byte of data, as follows:
CTXP0 to CTXD0..7, CTXP1 to CTXD8..15, CTXP2 to
CTXD16..23, and CTXP3 to CTXD24..31. Control bit
TXPMODE (Transmit Parity MODE) alters the normal
meaning of CTXP3. TXPMODE low is the normal mode,
where CTXP3 checks for parity for CTXD24..31. With
TXPMODE high, CTXP3 checks for parity for
CTXD24..31 and CTXC0. CTXC0 is a control input
which indicates whether CTXD0..31 is data or an
ordered set. An ordered set is a Fibre Channel word
where the most significant byte is composed of a valid
special character, K28.5, as defined in the standard.
Appendix A includes a table of valid special characters.
The parity bits follow odd parity convention, where it is
high if the number of ones is even and low if the
number of ones is odd.
For additional information and latest specifications, see our website: www.triquint.com
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