DG411L Просмотр технического описания (PDF) - Vishay Semiconductors

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DG411L

Precision Monolithic Quad SPST Low-Voltage CMOS Analog Switches

Vishay Semiconductors 

SCHEMATIC DIAGRAM (TYPICAL CHANNEL)

DG411L/412L/413L

Vishay Siliconix

V+

VL

VIN

GND

V-

TEST CIRCUITS

Level

Shift/

Drive

Figure 1.

S

V-

V+

D

VL

VL

VS

S

IN

GND

V+

V+

D

V-

V-

RL

300 Ω

VO

CL

35 pF

Logic

3V

Input

0V

Switch

Input*

VS

Switch

Output

Switch

Input*

0V

VO

- VS

50%

tr < 20 ns

tf < 20 ns

tON

VO

90 %

tON

90 %

CL (includes fixture and stray capacitance)

VO = VS

RL

RL + rDS(on)

Note: Logic input waveform is inverted for switches that

have the opposite logic sense control

Figure 2. Switching Time

VL

VS1

S1

IN1

VS2

S2

IN2

GND

V+

D1

D2

VO2

VO1

RL1

300 Ω

CL1

35 pF

V-

RL2

300 Ω

CL2

35 pF

Logic

3V

Input

0V

VS1

VO1

Switch

0V

Output

VS2

VO2

Switch

0V

Output

50 %

90 %

90 %

tD

tD

V-

CL (includes fixture and stray capacitance)

Figure 3. Break-Before-Make (DG413L)

Document Number: 71397

S-71241–Rev. E, 25-Jun-07

www.vishay.com

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