CMX644A Просмотр технического описания (PDF) - CML Microsystems Plc

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CMX644A

V.22 and Bell 212A Modem

CML Microsystems Plc 

V22 and Bell 212A Modem

CMX644A

Received data from the PSK Demodulator goes into the receive part of the UART block, where it is handled in

one of two ways depending on the setting of bit 5 of the UART MODE Register:

If bit 5 of the UART MODE Register is ‘0’ (‘Sync’ mode) then the receive part of the UART block will

simply take 8 consecutive bits from the Demodulator and transfer them to the RX DATA BYTE

Register (the first bit going into the D0 position).

If bit 5 of the UART MODE Register is ‘1’ (‘Async’ mode) then the received data output of the PSK

Demodulator is treated as asynchronous characters each comprising:

A Start bit (Space).

7 or 8 Data bits as determined by bit 0 of the UART MODE Register. These bits will be

placed into the RX DATA BYTE Register with the first bit received going into the D0 position.

An optional Parity bit as determined by bits 1 and 2 of the UART MODE Register. If Parity is

enabled (bit 2 of the UART MODE Register = ‘1’) then bit 7 of the FLAGS Register will be set

to ‘1’ if the received parity is incorrect.

Any number of Stop bits (Mark).

Bit 3 (RX DATA READY) of the FLAGS Register will be set to ‘1’ every time a new received value is loaded

into the RX DATA BYTE Register. If the previous contents of the RX DATA BYTE Register had not been read

out over the ‘C-BUS’ before the new value is loaded from the UART then bit 4 (RX DATA OVERFLOW) of the

FLAGS Register will also be set to ‘1’.

Figure 4b Receive UART Function (Async)

The C-BUS serial clock should be fast enough to ensure that an RX DATA READY interrupt is serviced

completely within a time which is less than 8 bit-times at 1200 baud, i.e. in less than 6.67ms.

© 2000 Consumer Microcircuits Limited

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D/644A/6

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