CDS-1401MM Просмотр технического описания (PDF) - Murata Power Solutions
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CDS-1401MM Datasheet PDF : 8 Pages
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CDS-1401
POWER REQUIREMENTS
Power Supply Ranges
+15V Supply
–15V Supply
+5V Supply
Power Supply Currents
+15V Supply
–15V Supply
+5V Supply
Power Dissipation
Power Supply Rejection
MIN.
+25°C
TYP.
MAX.
0 to +70°C
MIN. TYP. MAX.
–55 to +125°C
MIN. TYP. MAX.
UNITS
+14.75 +15.0 +15.25 +14.75 +15.0 +15.25 +14.75 +15.0 +15.25 Volts
–14.75 –15.0 –15.25 –14.75 –15.0 –15.25 –14.75 –15.0 –15.25 Volts
+4.75
+5.0
+5.25 +4.75
+5.0
+5.25 +4.75
+5.0
+5.25
Volts
—
+23
+27
—
+23
+27
—
+23
+27
mA
—
–23
–27
—
–23
–27
—
–23
–27
mA
—
+1
+2
—
+1
+2
—
+1
+2
mA
—
700
850
—
700
850
—
700
850
mW
—
100
—
—
100
—
—
100
—
dB
GENERAL DESCRIPTION (continued)
at the output of the CDS-1401 every 800ns. This correlates
with the fact that an acquisition time of 400ns is required for
each internal S/H amplifier (10V step setting to ±0.003%). The
input and output of the CDS-1401 can swing up to ±10 Volts.
The functionally complete CDS-1401 is packaged in a single,
24-pin, ceramic DDIP. It operates from ±15V and +5V supplies
and consumes 700mW. Though the CDS-1401’s approach to
CDS appears straightforward (see Description of Operation),
the circuit actually exploits an elegant architecture whose
tradeoffs enable it to offer wide-bandwidth, low-noise and high-
throughput combinations unachievable until now. The CDS-
1401 is a generic type of circuit that can be used with almost
any 10 to 14-bit A/D converter. However, DATEL does offer
A/D converters that are optimized for use with the CDS-1401.
TECHNICAL NOTES
1. To achieve specified performance, all power supply pins
should be bypassed with 2.2µF tantalum capacitors in
parallel with 0.1µF ceramic capacitors. All ANALOG
GROUND (pins 5, 14, 21 and 23) and DIGITAL GROUND
(pin 15) pins should be tied to a large analog ground plane
beneath the package.
2. In the CDS configuration, to avoid saturation of the S/H
amplifiers, the maximum analog inputs and conditions are
as follows:
ANALOG INPUT 1 < ±12V
(ANALOG INPUT 1 – ANALOG INPUT 2) < ±12V
3. The combined video and reference/offset signal from the
CCD array must be applied to S/H2, while the reference/
offset signal is applied to S/H1.
4. To use as a CDS circuit, tie pin 8 (S/H2 SUMMING NODE)
to either pin 6 (S/H1 OUT), through a 200 Ohm
potentiometer, or directly to pin 7 (S/H1 ROUT). In both
cases, the CCD's output is tied to pins 3 (ANALOG INPUT
1) and 4 (ANALOG INPUT 2). As shown in Figure 5, the
200Ω potentiometer is for gain matching.
5. To use as a dual S/H, leave pin 7 (S/H1 ROUT) and pin 8
(S/H2 SUMMING NODE) floating. Pin 6 (S/H1 OUT) will be
the output of S/H1 and pin 22 (V OUT) will be the output
of S/H2.
6. See Figure 4 for acquisition time versus accuracy and input
voltage step amplitude.
FUNCTIONAL DESCRIPTION
Correlated Double Sampling
All photodetector elements (photodiodes, photomultiplier tubes,
focal plane arrays, charge coupled devices, etc.) have unique
output characteristics that call for specific analog-signal-
processing (ASP) functions at their outputs. Charge coupled
devices (CCD’s), in particular, display a number of unique
characteristics. Among them is the fact that the “offset error”
associated with each individual pixel (i.e., the apparent
photonic content of that pixel after having had no light incident
upon it) changes each and every time that particular pixel is
accessed.
Most of us think of an offset as a constant parameter that
either can be compensated for (by performing an offset
adjustment) or can be measured, recorded, and subtracted
from subsequent readings to yield more accurate data.
Contending with an offset that varies from reading to reading
requires measuring and recording (or capturing and storing)
the offset each and every time, so it can be subtracted from
each subsequent data reading.
The “double sampling” aspect of CDS refers to the operation of
sampling and storing/recording a given pixel’s offset and then
sampling the same pixel’s output an instant later (with both the
offset and the video signal present) and subsequently
subtracting the two values to yield what is referred to as the
“valid video” output for that pixel.
The “correlated” in CDS refers to the fact that the two samples
must be taken close together in time because the offset is
constantly varying. Reasons for this phenomena are
discussed below.
At the output of all CCD’s, transported pixel charge (electrons)
is converted to a voltage by depositing the charge onto a
capacitor (usually called the output or “floating” capacitor).
The voltage that develops across this capacitor is obviously
proportional to the amount of deposited charge (i.e., the
number of electrons) according to ∆V = ∆Q/C. Once settled,
the resulting capacitor voltage is buffered and brought to the
CCD’s output pin as a signal whose amplitude is proportional
to the total number of photons incident upon the relevant pixel.
After the output signal has been recorded, the floating
capacitor is discharged (“reset”, “clamped”, “dumped”) and
made ready to accept charge from the next pixel. This is
when the problems begin. (This is a somewhat oversimplified
3
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