M5M467805BTP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC
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M5M467805BTP Datasheet PDF : 39 Pages
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(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
~ CAPACITANCE (Ta=0 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted)
Symbol
Parameter
Test conditions
CI (A)
CI (OE)
CI (W)
CI (RAS)
CI (CAS)
CI / O
Input capacitance,address inputs
Input capacitance, OE input
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports
VI=Vss
f=1MHZ
Vi=25mVrms
Limits
Unit
Min Typ Max
5
pF
7
pF
7
pF
7
pF
7
pF
7
pF
SWITCHING CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Limits
Symbol
Parameter
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S Unit
M5M465165B-5,5S M5M465165B-6,6S
Min
Max
Min
Max
tCAC
Access time from CAS
(Note 7,8)
13
15
ns
tRAC
Access time from RAS
(Note 7,9)
50
60
ns
tAA
Column address access time
(Note 7,10)
25
30
ns
tCPA
Access time from CAS precharge
(Note 7,11)
28
33
ns
tOEA
Access time from OE
(Note 7)
13
15
ns
tOHC
Output hold time from CAS
5
5
ns
tOHR
Output hold time from RAS
(Note 13)
5
5
ns
tCLZ
Output low impedance time from CAS low (Note 7)
5
5
ns
tOEZ
Output disable time after OE high
(Note 12)
13
15
ns
tWEZ
Output disable time after W high
(Note 12)
13
15
ns
tOFF
Output disable time after CAS high
(Note 12,13)
13
15
ns
tREZ
Output disable time after RAS high
(Note 12,13)
13
15
ns
Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing RAS-only refresh or CAS before RAS refresh).
Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are VOH=2.0V and VOL=0.8V.
8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max) and tCP ≥ tCP(max).
9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
12: tOEZ(max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ ± 10 µA) and is
not reference to VOH(min) or VOL(max).
13: Output is disabled after both RAS and CAS go to high.
9
MITSUBISHI
Jun. 1999
ELECTRIC
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