M5M467805BTP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC
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M5M467805BTP Datasheet PDF : 39 Pages
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(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
(Note 24)
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
Limits
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S Unit
M5M465165B-5,5S M5M465165B-6,6S
Min
Max
Min
Max
84
104
ns
50
10000
60 10000 ns
8
10000
10 10000 ns
35
40
ns
13
15
ns
0
0
ns
8
10
ns
8
10
ns
8
10
ns
8
10
ns
0
0
ns
8
10
ns
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
OE hold time after W low
(Note23)
(Note24)
(Note24)
(Note24)
Limits
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S Unit
M5M465165B-5,5S M5M465165B-6,6S
Min
Max
Min
Max
109
133
ns
75 10000
89 10000 ns
38 10000
70
44 10000 ns
82
ns
38
44
ns
0
0
ns
28
32
ns
65
77
ns
40
47
ns
13
15
ns
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD (min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min)
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi-
nate.
11
MITSUBISHI
Jun. 1999
ELECTRIC
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