ACT-PD1M16W-070L4I Просмотр технического описания (PDF) - Aeroflex Corporation

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ACT-PD1M16W-070L4I

Fast Page Mode 16 Megabit Plastic Monolithic DRAM

Aeroflex Corporation 

WRITE ENABLE (WE)

The read or write mode is selected through

WE. A logic high on WE selects the read

mode and a logic low selects the write mode.

The data inputs are disabled when the read

mode is selected. When WE goes low prior to

xCAS (early write), data out remains in the

high-impedance state for the entire cycle,

permitting a write operation with OE

grounded.

DATA IN (I/O0-15)

Data is written during a write or

read-modify-write cycle. Depending on the

mode of operation, the falling edge of xCAS or

WE strobes data into the on-chip data latch.

In an early-write cycle, WE is brought low

prior to xCAS and the data is strobed in by the

first occurring xCAS with setup and hold times

referenced to this signal. In a delayed-write or

read-modify-write cycle, xCAS is already low

and the data is strobed in by WE with setup

and hold times referenced to this signal. In a

delayed-write or read-modify-write cycle, OE

must be high to bring the output buffers to the

high-impedance state prior to impressing data

on the I/O lines.

DATA OUT (I/O0-15)

Data out is the same polarity as data in. The

output is in the high-impedance (floating)

state until xCAS and OE are brought low. In a

read cycle, the output becomes valid after the

access time interval tCAC (which begins with

the negative transition of xCAS) as long as

tRAC and tAA are satisfied.

OUTPUT ENABLE (OE)*

OE controls the impedance of the output

buffers. When OE is high, the buffers remain

in the high-impedance state. Bringing OE low

during a normal cycle activates the output

buffers, putting them in the low-impedance

state. It is necessary for both RAS and xCAS

to be brought low for the output butters to go

into the low-impedance state, and they remain

in the low-impedance state until either OE or

xCAS is brought high.

*Output Enable can be held low during write cycles.

RAS-ONLY REFRESH

A refresh operation must be performed at

least once every 16ms (128ms for long

refresh periods) to retain data. This can be

achieved by strobing each of the 1024 rows

(A0-9). A normal read or write cycle refreshes

all bits in each row that is selected. A

RAS-only operation can be used by holding

both xCAS at the high (inactive) level,

conserving power as the output buffers

remain in the high-impedance state.

Externally generated addresses must be used

for a RAS-only refresh.

HIDDEN REFRESH

Hidden refresh can be performed while

maintaining valid data at the output pin. This

is accomplished by holding xCAS at VIL after

a read operation and cycling RAS after a

specified precharge period, similar to a

RAS-only refresh cycle. The external address

is ignored and the refresh address is

generated internally.

xCAS-BEFORE-RAS (xCBR)

REFRESH

xCBR refresh is utilized by bringing at least

one xCAS low earlier than RAS (see

parameter tCSR) and holding it low after RAS

fails (see parameter tCHR). For succesive

xCBR refresh cycles, xCAS can remain low

while cycling RAS. The external address is

ignored and the refresh address is generated

internally.

POWER UP

To achieve proper device operation, an initial

pause of 200µs followed by a minimum of

eight initialization cycles is required after

power up to full Vcc level. These eight

initialization cycles must include at least one

refresh (RAS-only or xCBR) cycle.

Aeroflex Circuit Technology

7

SCD3750 REV A 8/31/98 Plainview NY (516) 694-6700

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