PI74FCT162511TA Просмотр технического описания (PDF) - Pericom Semiconductor
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PI74FCT162511TA Datasheet PDF : 8 Pages
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PI74FCT16511/162511T
16-BIT REGISTERED/
123456789012345678901234567890121234567890123456789012345678901212345678901234L56A789T01C23H45E678D901T21R23A45N67S89C01E234I5V67E89R012W345I6T789H012P12A34R56I7T89Y012
Truth Table(1,2)
Inputs
OEAB LEAB CLKAB
AX
H
X
X
X
L
H
X
L
L
H
X
H
L
L
↑
L
L
L
↑
H
L
L
L
X
L
L
H
X
Output
Buffers
BX
Z
L
H
L
H
B(3)
B(4)
NOTES:
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care or Irrelevant
Z = High Impedance
↑ = LOW-to-HIGH Transition
2. A-to-B data flow is shown. B-to-A flow control is the same, except using
OEBA, LEBA, and CLKBA.
3. Output level before the indicated steady-state input conditions were
established.
4. Output level before the indicated steady-state input conditions were
established, assuming CLKAB was HIGH before LEAB went LOW.
Truth Table (Parity Generation) (1, 2, 3, 4, 5)
A0 - A7, Total Number of Inputs that are high
1, 3, 5 or 7
1, 3, 5 or 7
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
ODD/EVEN
L
H
L
H
NOTES:
1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H.
2. A-to-B parity generation is shown. B-to-A can check parity while A-to-B is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L, then CLKAB will control as an edge triggered clock.
4. Conditions shown are for the byte A0-A7. The byte A8-A15 is similar but will output the parity on PB2.
5. The error flag PERB will remain in a high state during parity generation.
PB1
H
L
L
H
Truth Table (Parity Checking) (1, 2, 3, 4)
A0 - A7 and PA1(5), Total Number of Inputs that are high
1, 3, 5, 7 or 9
1, 3, 5, 7 or 9
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
ODD/EVEN
L
H
L
H
PERB
L
H(6)
H(6)
L
NOTES:
1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A parity checking is same but uses OEBA = L, OEAB = H and errors will be indicated on PERA.
3. In parity checking mode the parity bits will be transmitted unchanged along with the corresponding data regardless of parity errors. (PB1 = PA1)
4. The response shown is for LEAB = H. If LEAB = L, then CLKAB will control as an edge triggered clock.
5. Conditions shown are for the byte A0-A7 and PA1. The byte A8-A15 and PA2 is same.
6. The parity error flag PERB is a combined flag for both bytes A0-A7 and A8-A15. If a parity error occurs on either byte PERB will go low.
4
PS2080A 01/15/95
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