AS5SS128K36 Просмотр технического описания (PDF) - Austin Semiconductor
Номер в каталоге
Компоненты Описание
производитель
AS5SS128K36 Datasheet PDF : 16 Pages
| |||
Austin Semiconductor, Inc.
PIN ASSIGNMENT
(Top View)
100-pin TQFP (DQ)
SRAM
AS5SS128K36
DQc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
VSS
VDD
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQd
1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
2
80
3
79
4
78
5
77
6
76
7
75
8
74
9
73
10
72
11
71
12
70
13
69
14
68
15
67
16
66
17
65
18
64
19
63
20
62
21
61
22
60
23
59
24
58
25
57
26
56
27
55
28
54
29
53
30
52
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
DQb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
VSS
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQa
PIN DESCRIPTIONS
TQFP PINS
37
36
32-35, 44-50,
81, 82, 99, 100
SYMBOL
SA0
SA1
SA
93
BWa\
94
BWb\
95
BWc\
96
BWd\
87
CKE\
88
R/W\
TYPE
Input
Input
Input
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as
address bits for the higher-density 8Mb and 16Mb ZBL SRAMs, respectively. SA0 and
SA1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to
be written when a WRITE cycle is active and must meet the setup and hold times
around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle
as the address. BWa\ controls DQa pins; BWb\ controls DQb pins; BWc\ controls
DQc pins; BWd\ controls DQd pins.
Synchronous Clock Enable: This active LOW input permits CLK to propagate
throughout the device. When CKE is HIGH, the device ignores the CLK input and
effectively internally extends the previous CLK cycle. This input must meet setup and
hold times around the rising edge of CLK.
Read/Write: This input determines the cycle type when ADV/LD\ is LOW and is the
only means for determining READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin
permits BYTE WRITE operations and must meet the setup and hold times around the
rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW.
AS5SS128K36
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
Share Link: 