Z80180 Просмотр технического описания (PDF) - Zilog

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Z80180

ENHANCED Z180 MICROPROCESSOR

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Z80180/Z8S180/Z8L180

Enhanced Z180 Microprocessor

Notes: All Signals with a preceding front slash, “/” are ac-

tive Low, for example, B//W (WORD is active Low); /B/W

(BYTE is active Low, only). Alternatively, an overslash

may be used to signify active Low, for example WR

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Power connections follow conventional descriptions be-

low:

Connection

Power

Ground

Circuit

VCC

GND

Device

VDD

VSS

Ø

Timing

Generator

A18/TOUT

TXS

RXS/CTS1

CKS

16-bit

Programmable

Reload Timers

(2)

Clocked

Serial I/O

Port

MMU

Bus State Control

CPU

DMACS

(2)

Asynchronous

SCI

(Channel 0)

Asynchronous

SCI

(Channel 1)

Interrupt

/DREQ1

TEND1

TXA0

CKA0, /DREQ0

RXA0

/RTS0

/CTS0

/DCD0

TXA1

CKA1, /TEND0

RXA1

Address

Buffer

Data

Buffer

VCC

VSS

A19-A0

D7-D0

Figure 1. Z80180/Z8S180/Z8L180 Functional Block Diagram

1-2

PRELIMINARY

DS971800401

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