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ADMC331-ADVEVALKIT

Single Chip DSP Motor Controller

Analog Devices 

ADMC331–SPECIFICATIONS (VDD = +5 V ؎ 10%, GND = SGND = 0 V, TA = –40؇C to +85؇C, unless otherwise noted)

Parameter

Min Typ Max

Units Conditions/Comments

ANALOG-TO-DIGITAL CONVERTER

Signal Input

Resolution

Converter Linearity

Zero Offset

Channel-to-Channel Comparator Match

Comparator Delay

Current Source

Current Source Linearity

0.3

3.31

122

2

12

5

50

22

600

10.16 12.7 15.24

2

V

Bits

LSBs

mV

mV

ns

µA

%

Charging Capacitor = 1000 pF

2.5 kHz Sample Frequency

No Missing Codes

ELECTRICAL CHARACTERISTICS

VIL Logic Low

0.8

VIH Logic High

2

VOL Low Level Output Voltage

0.4

VOL Low Level Output Voltage (XTAL)

0.5

VOH High Level Output Voltage

4

IIL Low Level Input Current

–10

IIH High Level Input Current

10

IIH Hi-Level PWMTRIP, PIO0–PIO23 Current

100

IIH Hi-Level PWMPOL/PWMSR Current

10

IIL Lo-Level PWMTRIP, PIO0–PIO23 Current

10

IIL Lo-Level PWMPOL/PWMSR Current

100

IDD Supply Current (Dynamic)

120

IDD Supply Current (Idle)

60

REFERENCE VOLTAGE OUTPUT

Voltage Level

Output Voltage Change TMIN to TMAX

2.2 2.55 2.9

20

16-BIT PWM TIMER

Counter Resolution

Edge Resolution (Single Update Mode)

Edge Resolution (Double Update Mode)

Programmable Deadtime Range

Programmable Deadtime Increments

Programmable Pulse Deletion Range

Programmable Pulse Deletion Increments

PWM Frequency Range

PWMSYNC Pulsewidth (TCRST)

Gate Drive Chop Frequency Range

16

76.9

38.5

0

78

76.9

0

78

76.9

0.198

0.077

9.8

0.02

6.5

V

V

V

V

V

µA

µA

µA

µA

µA

µA

mA

mA

V

mV

Bits

ns

ns

µs

ns

µs

ns

kHz

µs

MHz

IOL = 2 mA

IOL = 2 mA

IOH = 0.5 mA

VIN = 0 V

VIN = VDD

@ VDD = max, VIN = VDD max

@ VDD = max, VIN = VDD max

@ VDD = max, VIN = 0 V

@ VDD = max, VIN = 0 V

13 MHz DSP Clock

13 MHz DSP Clock

100 µA Load

13 MHz CLKIN

13 MHz CLKIN

13 MHz CLKIN

13 MHz CLKIN

13 MHz CLKIN

13 MHz CLKIN

13 MHz CLKIN

13 MHz CLKIN

13 MHz CLKIN

AUXILIARY PWM TIMERS

Resolution

PWM Frequency

8

0.051

6.5

Bits

MHz

13 MHz CLKIN

NOTES

1Signal input max V = 3.5 V if VDD = 5 V ± 5%.

2Resolution varies with PWM switching frequency (13 MHz Clock in Double Update mode), 50.7 kHz = 9 bits, 6.3 kHz = 12 bits.

Specifications subject to change without notice.

–2–

REV. B

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