ADMC300 Просмотр технического описания (PDF) - Analog Devices
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ADMC300 Datasheet PDF : 42 Pages
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ADMC300–SPECIFICATIONS
ENCODER INTERFACE UNIT (VDD = AVDD = 5 V ؎ 10%, GND = AGND = 0 V, TAMB = –40؇C to +85؇C, CLKIN = 12.5 MHz, unless
otherwise noted)
Parameter
Test Conditions
Min Typ Max
Unit
fENC, MAX
Maximum Encoder Pulse Rate1
3.1
MHz
NOTES
1Assumes perfect quadrature encoder signals.
Specifications subject to change without notice.
AUXILIARY PWM OUTPUTS (VDD = AVDD = 5 V ؎ 10%, GND = AGND = 0 V, TAMB = –40؇C to +85؇C, CLKIN = 12.5 MHz, unless
otherwise noted)
Parameter
fAUXPWM
Resolution
Switching Frequency
Specifications subject to change without notice.
Test Conditions
Min Typ
8
48.8
Max
Unit
Bits
kHz
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals
tCK is defined as 0.5 tCKI. The ADMC300 uses an input clock with a frequency equal
to half the instruction rate; a 12.5 MHz input clock (which is equivalent to 80 ns)
yields a 40 ns processor cycle (equivalent to 25 MHz). tCK values within the range of
0.5 tCKI period should be substituted for all relevant timing parameters to obtain
specification value.
Example: tCKH = 0.5 tCK – 10 ns = 0.5 (40 ns) – 10 ns = 10 ns.
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
Switching Characteristics:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
80
150
ns
20
ns
20
ns
0.5 tCK – 10
ns
0.5 tCK – 10
ns
0
20
ns
Control Signals
Timing Requirement:
tRSP
RESET Width Low
5 tCK1
ns
PWM Shutdown Signals
Timing Requirements:
tPWMTPW
PWMTRIP Width Low
tPIOPWM
PIO Width Low
3 tCK
ns
3 tCK
ns
NOTES
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
Specifications subject to change without notice.
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 1. Clock Signals
–4–
REV. B
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