AD7008AP20 Просмотр технического описания (PDF) - Analog Devices
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AD7008AP20 Datasheet PDF : 16 Pages
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AD7008
Parallel Configuration
The AD7008 functions fully in the parallel mode. There are
two parallel modes of operation. Both are similar but are tai-
lored for different bus widths, 8 and 16 bits. All modes of op-
eration can be controlled by the parallel interface.
On power up and reset, the chip must be configured by instruc-
ting the command register how to operate. The command reg-
ister may be used to set the device up for 8- or 16-bit mode,
DMDXX–DATA BITS
DMAXX–ADDRESS BITS
U1
74HC138
+5V
DMS1
DMWR
6
4
5
G1
G2A
G2B
DMA02
DMA01
DMA00
3
2
1
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
7
9
10
11
12
13
14
15
DMD24
DMD25
DMD26
DMD27
DMD28
DMD29
DMD30
DMD31
DMD32
DMD33
DMD34
DMD35
DMD36
DMD37
DMD38
DMD39
GND
DMD36
DMD37
DMD38
DMD39
+5V
U2
14 50MHz
VCC
RESET
8
OUT
U3
AD7008
C1
19
20
21
22
23
24
25
26
8
9
10
11
12
13
14
15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
16 WR
27 CS
32
33
34
35
36
41
42
31
30
38
37
TC0
TC1
TC2
TC3
LOAD
SCLK
SDATA
FSELECT
CLK
RESET
SLEEP
VREF
COMP
IOUT
IOUT
FSADJUST
VAA
VDD
VDD
VDD
AGND
DGND
DGND
DGND
DGND
TEST
6
+5V
0.1µF C2
5
+5V
0.1µF
2 R4
49.9
1
R3
49.9
4
R5
390
3 +5V
17 +5V
28 +5V
39 +5V
44
7
18
29
43
40
VEE
7 K1115
Figure 12. Parallel Interface to a 16- or 32-Bit DSP or
Microprocessor
AD7008
10 BITS
RSET
390Ω
sleep mode, amplitude control and synchronization logic. At
reset, the chip defaults to 8-bit bus, no amplitude control and
logic synchronized. The code fragment below indicates how
the initialization code for the AD7008 might look using the
ADSP-21020.
{dds_para is a port define to decode for
the parallel assembly register write pulse.
dds_cont is a port defined to decode for
the TC control Load pin. The Command reg-
ister must first be loaded with configura-
tion information. In this example, the chip
is set up for 16 bits data. See Table III
for details.}
r4 = 0x00010000; {16 bits, Normal Op., AM
disabled, Synchronizer
enabled}
dm(dds_para) = r4; {write data to parallel
assembly register}
r4 = 0x00000000;
dm(dds_cont) = r5; {No data written, data is
just transferred from
parallel assembly
register to the command
register}
r4 = 0x051E0000; {1 MHz=051EB852, load high
word first}
dm(dds_para) = r4;
r4 = 0xB8520000; {Now load low word}
dm(dds_para)=r4;
r4 = 0x80000000; {Transfer data from the
parallel assembly
register to Freq0}
dm(dds_cont)=r4;
Local Oscillator
The AD7008 is well suited for applications such as local oscilla-
tors used in super-heterodyne receivers. Although the AD7008
can be used in a variety of receiver designs, one simple local os-
5Ω
5Ω
FILTER
0.1µF
–16dBm
RF
INPUT
(ANTENNA)
BANDPASS
FILTER
330Ω
330Ω
4.7
100
100
µF
nF
nF
10Ω
VMID
10Ω
OPTIONAL
BPF
OR LPF
0°
PLL
90°
AM OUTPUT
PLL INPUT
FM OUTPUT
MIDPOINT
BIAS
GENERATOR
AD607
BIAS
CIRCUIT
AGC VOLTAGE
AGC
DETECTOR
PTAT
VOLTAGE
RECEIVED
SIGNAL
STRENGTH
INDICATOR
Figure 13. AD7008 and AD607 Receiver Circuit
–10–
REV. B
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