LC75412E Просмотр технического описания (PDF) - SANYO -> Panasonic
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производитель
LC75412E Datasheet PDF : 21 Pages
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LC75412E, 75412W
Parameter
[Fader Block]
Input resistance
Symbol
Pin Name
Rfed LFIN, RFIN
Step setting error
ATerr
L/R balance
[General]
Total harmonic distortion
Input crosstalk
L/R crosstalk
Maximum attenuated output
Output noise voltage
Current drain
Input high-level current
Input low-level current
Maximum input voltage
Common-mode rejection ratio
BAL
THD (1) VIN = 0dBV, f = 1 kHz
THD (2) VIN = –10dBV, f = 10 kHz
CT VIN = 1Vrms, f = 1 kHz
CT VIN = 1Vrms, f = 1 kHz
Vomin (1) VIN = 1Vrms, f = 1 kHz
Vomin (2)
VIN = 1Vrms, f = 1 kHz
INMUTE, fader –∞
VN (1)
VN (2)
Flat overall, IHF-A filter
Flat overall, 20 to 20 kHzBPF
IDD
IIH
IIL
VCL
CMRR
CL, DI, CE, VIN = 9 V
CL, DI, CE, VIN = 0 V
THD = 1%, RL = 10 kΩ
flat overall, fIN = 1 kHz
VIN = 0 dB, f = 1 kHz
Conditions
0dB to –2dB
–2dB to –20dB
–20dB to –30dB
–30dB to –60dB
Ratings
Unit
min
typ
max
25
50
100
kΩ
±0.5
dB
±1
dB
±2
dB
±3
dB
±0.5
dB
0.004
0.006
80
88
80
88
80
88
90
95
5
7
55
–10
2.3
2.5
70
0.01
%
0.01
%
dB
dB
dB
dB
10
µV
15
µV
60 mA
10
µA
µA
Vrms
dB
Control Timing and Data Format
To control the LC75412E and LC75412W input specified serial data to the CE, CL, and DI pins.
The data configuration consists of a total of 52 bits broken down into 8 address bits and 44 data bits.
CE
DI
B0 B1 B2 B3 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5
CL
D38 D39 D40 D41 D42 D43
CE
1µs 1µs 1µs
1µs
min min min
min
1µs
CL
min
DI
1µs min ≤ TDEST
No. 7053-5/21
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