MT34013 Просмотр технического описания (PDF) - Aeroflex Corporation
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MT34013 Datasheet PDF : 8 Pages
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MT34013
NOT CSTR and NOT OS must be high during reset but may go low immediately NOT RESET is removed.
NOT CSTR, LOW min = HIGH min = 1.5T for correct operation CO-3, SET UP TIME = 0, HOLD TIME = 2T min
after NOT CSTR goes low.
NOT CSTR is synchronised by ØIN to give a 0.5T interval strobe pulse. This pulse disables the state decoder O/P’s
allowing 0.5T settling time for the new state to be established before re-enabling the O/P’s. This ensures that data
I/P’s cannot be internally shorted together when changing from test on one channel to another.
*T = 1/f = 1 clock cycle time of ØIN.
A single phase clock must be provided by the user with a frequency in the range of 1.25 - 2.0 MHZ. The chip will
accommodate all the selectable channel speed options available with the clock at any frequency between these limits.
A 3 bit binary code is allocated in the first word of output data to signify which channel has received a message and is
being accessed.
The positioning of the code is shown in fig 2 and has the form shown below:-
1st output word bit number
12
11
10
0
0
0
Channel 0
0
0
1
Channel 1
0
1
0
Channel 2
0
1
1
Channel 3
1
0
0
Channel 4
1
0
1
Channel 5
1
1
0
Channel 6
1
1
1
Channel 7
FIG. 1
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
4
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