MT34013 Просмотр технического описания (PDF) - Aeroflex Corporation
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MT34013 Datasheet PDF : 8 Pages
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MT34013
Prioritised error information for each channel is latched into a 3 bit register with the format indicated in Table 1 and
made available at the user output port.
Channel servicing is carried out on a rotating priority basis, where the last channel serviced is given the lowest
priority, in order to allow full access for each channel.
A facility is provided on the decoder chip to enable individual channels to be tested, which consists of a multi-plexer
on the input to each channel to allow test messages (generated external to the chip) to be injected.
TABLE 1
Prioritorised coded error data.
Bit position relative to first output word see fig.2.
15
14
13
1
1
1
)
1
1
0
)
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
Unused
Interconnection fault (highest priority)
Channel overrun (causes corruption of following word in that channel.
Word length error (number of bits not equal to 32).
Parity error (word received with even parity).
Service overrun (not all words or bytes accessed) - lowest priority.
Good word.
USER INTERFACE
Arinc 429 data is read from the decoder chip via an 8 or 16 bit parallel data bus.
Fig 2 illustrates the formatting of the output data relative to the generalised Arinc 429 word format.
Control of the chip is achieved via a four bit control port which provides the user with the facilities outlined in Table
2. The control word is strobed into the chip using the leading edge of the NOT CSTR input providing the required set
up and hold times are met.
N.B. NOT CSTR must be high before NOT RESET is removed.
DATA READY signifies to the user that a word is available and can be accessed by pulling NOT CHIP ENABLE low
and strobing the NOT OUTPUT SELECT line as illustrated in fig .3.
NOT RESET provides the user with a simple means of asynchronously inhibiting the chip. Activating NOT RESET
disables the output buffers and clears DATA READY asynchronously. The internal counters are cleared by holding
NOT RESET low for 2 clock periods. Default options are selected which can be overwritten using the control input
port. The default options are shown below and are selected by pulsing RESET low or by selecting software reset (see
table 2).
• Channel sequencer set to channel 0 for highest priority.
• All channels are set for low speed operation.
• All channels are set for normal reception with no end around test mode.
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
3
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