UDA1343 Просмотр технического описания (PDF) - Philips Electronics

Номер в каталоге

Компоненты Описание

производитель

UDA1343

Economy audio CODEC with features

Philips Electronics 

Philips Semiconductors

Economy audio CODEC with features

Preliminary specification

UDA1343TT

Data write mode

For writing data to a device four bytes must be sent.

The data write mode is illustrated in Fig.8.

1. One byte with the device address including ‘01’ for

signalling write to the device.

2. One byte starting with a logic 0 for signalling write

followed by 7 bits indicating the destination address.

3. Two data bytes.

Notes:

1. Each time a new destination address needs to be

written, the device address must sent again.

2. When addressing the device for the first time after

power-up of the device, at least one L3 clock cycle

must be sent to enable the L3 interface.

Data read mode

For reading from the device, a prepare-read must first be

done. After the prepare-read, the device address is sent

again. The device then returns with the register address,

indicating whether the address was valid or not, and the

data of the register. This procedure is explained below,

and an example transmission is illustrated in Fig.9.

1. One byte with the device address including ‘01’ for

signalling write to the address.

2. One byte is sent with the register address which needs

to be read. This byte starts with a logic 1, which

indicated that there will be a read action from the

register.

3. One byte with the device address including ‘11’ is sent

to the device. The ‘11’ indicates that the device must

write data to the microcontroller.

4. The device now writes the requested register address

to the bus, indicating whether the requested register

was valid or not (logic 0 means valid, logic 1 means

invalid).

5. The device writes the data from the requested register

to the bus (two bytes).

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

2000 Jan 12

th(L3)A

tsu(L3)A

tCLK(L3)L

tCLK(L3)H

tsu(L3)DA

BIT 0

th(L3)DA

tsu(L3)A

th(L3)A

Tcy(CLK)(L3)

BIT 7

MGL723

Fig.6 Timing address mode.

13

Share Link: