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28L202A1B

Dual universal asynchronous receiver/transmitter (DUART)

Philips Electronics 

Philips Semiconductors

Dual universal asynchronous receiver/transmitter

(DUART)

Objective specification

SC28L202

Designed for “Glueless operation in 68XXX and X86 environments”

DESCRIPTION

The 28L202 is a high performance functional upgrade for the Philips

dual channel UARTS. The SCC2692 and SC26C92 operating at 3.3

or 5 volts supply with added features and deeper partitioned FIFOs.

Its configuration on power up is similar that of the SC26C92. Its

differences from the SC26C92 are: 256 character receiver, 256

character transmit FIFOs, CRC error detection, 3 and 5 volt

compatibility, 8 I/O ports for each UART. IRDA compatibility,

arbitrating interrupt system and overall faster buss and data speeds.

It is fabricated in an advanced CMOS process that allows stand by

current of less that one microampere.

Pin programming will allow the device to operate with either the

Motorola or Intel bus interface by changing the function of some

pins. (Reset is inverted, DACKN enabled for example).

The Philips Semiconductors 28L202 Dual Universal Asynchronous

Receiver/Transmitter (DUART) is a single-chip CMOS–LSI

communications device that provides two full-duplex asynchronous

receiver/transmitter channels in a single package. It interfaces

directly with microprocessors and may be used in a polled or

interrupt driven system.

The operating mode and data format of each channel can be

programmed independently. Additionally, each receiver and

transmitter can select its operating speed as one of twenty-three

fixed baud rates; a 16X clock derived from a programmable

counter/timer, or an external 1X or 16X clock. The baud rate

generator and counter/timer can operate directly from a crystal or

from external clock inputs. The ability to independently program the

operating speed of the receiver and transmitter make the DUART

particularly attractive for dual-speed channel applications such as

clustered terminal systems.

Each receiver and transmitter is buffered by eight character FIFOs

to minimize the potential of receiver overrun, transmitter underrun

and to reduce interrupt overhead in interrupt driven systems. In

addition, a flow control capability is provided to disable a remote

transmitter when the receiver buffer is full.

Also provided on the 28L202 are a multipurpose 7-bit input port and

a multipurpose 8-bit output port. These can be used as

general-purpose I/O ports or can be assigned specific functions

(such as clock inputs or status/interrupt outputs) under program

control.

The 28L202 are available in two package versions: a 44-pin PLCC

and 44-pin plastic quad flat pack (PQFP).

FEATURES

• 3.3 or 5.0 volt operation

• Dual full-duplex independent asynchronous receiver/transmitters

• 256 or larger character FIFOs for each receiver and transmitter

• Power up as 8 bit data no parity one stop bit 9600 baud

• Pin programming (PQFP package) to 68K or 80xxx bus interface

• Programmable data format

– 5 to 8 data bits plus parity

– Odd, even, no parity or force parity

– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments

• 16-bit programmable Counter/Timer

• Programmable baud rate for each receiver and transmitter

selectable from:

– 23 fixed rates: 50 to 230.4k baud

– Other baud rates to MHz at 16X

– Programmable user-defined rates derived from a

programmable Counter/timer

– External 1X or 16X clock

• Parity, framing, and overrun error detection

• False start bit detection

• Line break detection and generation

• Programmable channel mode

– Normal (full-duplex)

– Automatic echo

– Local loop back

– Remote loop back

– Multi-drop mode (also called ‘wake-up’ or ‘9-bit’)

• Multi-function 7-bit input port

– Can serve as clock or control inputs

– Change of state detection on eight inputs

– Inputs have typically >100k pull-up resistors

• Multi-function 8-bit output port

– Individual bit set/reset capability

– Outputs can be programmed to be status/interrupt signals

• Versatile interrupt system

– Single interrupt output with eight maskable interrupting

conditions

– Output port can be configured to provide a total of up to six

separate interrupt outputs that may be wire ORed.

– Each FIFO can be programmed for four different interrupt

levels.

– Watch dog timer for each receiver

• Maximum data transfer rates:

– 1X – 1Mb/sec, 16X – 1Mb/sec

• Automatic wake-up mode for multi-drop applications

• Start-end break interrupt/status

• Detects break which originates in the middle of a character

• On-chip crystal oscillator

• Power down mode

• Receiver time-out mode

• Single +3.3V or +5V power supply

• Powers up to emulate SCC2692 and SC26C92

1998 Oct 05

2

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