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XR68C192IV

DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER

Exar Corporation 

XR68C92/192

COMMUNICATION CHANNELS A AND B

Each communication channel includes a full-duplex

asynchronous receiver/transmitter (UART). The operat-

ing frequency for each receiver and each transmitter can

be selected independently from the baud-rate genera-

tor, the C/T, or from an external clock. The transmitter

accepts parallel data from the CPU, converts it to a

serial bit stream, inserts the appropriate start, stop, and

optional parity bits, and outputs a composite serial

stream of data on the TX output pin. The receiver

accepts serial data on the RX pin, converts this serial

input to parallel format, checks for a start bit, stop bit,

parity bit (if any), or break condition, and transfers an

assembled character to the CPU during read opera-

tions.

INPUT PORT

The CPU reads the inputs to this 6-bit port (IP0 through

IP5). High or low inputs to the input port result in the

CPU reading a logic one or logic zero, respectively.

Each input port bit also has an alternate control function

capability. The alternate functions can be enabled/

disabled on a bit-by-bit basis.

1

Four change-of-state detectors are associated with

inputs IP0, IP1, IP2, and IP3. If a high-to-low or low-to-

high transition occurs on any of these inputs and the

new level is stable for more than 25 to 50 microsec-

onds (best-to-worst case times), the corresponding bit

in the input port change register (IPCR) will be set. The

sampling clock of the change detectors is the XTAL1/

96 tap of the baud-rate generator, which is 38.4kHz if

XTAL1 is 3.6864MHz. A new input level must be

sampled on two consecutive sample clocks to pro-

duce a change detect. Also, users can program the

XR68C92/192 to allow a change of state to generate

an interrupt to the CPU. The IPCR bits are cleared

when the CPU reads the register.

OUTPUT PORT

The 8 output port pins can either be used as a general-

purpose output port or can be controlled using internal

registers to generate signals representing various con-

ditions. Associated with the output port is an output port

register (OPR) that can be bit-wise programmed. A bit

is set (logical 1) by performing a write operation at

address 0xE with the data having that bit-location to be

1 (0 means no change). Similarly, a bit is reset (logical

0) by performing a write operation at address 0xF with

the data having that bit-location as 1 (0 means no

change). However, it is to be noted that the outputs are

complements of the data contained in the OPR (eg.,

0x05 in OPR actually means 0xFA at the output pins).

Besides general-purpose outputs, the outputs can be

individually assigned specific auxiliary functions serv-

ing the communication channels. The assignment is

accomplished by appropriately programming the

channel A and B mode registers (MR0A, MR0B,

MR1A, MR1B, MR2A, and MR2B) and the output port

configuration register (OPCR).

NOTE: The terms assertion and negation will be used

extensively to avoid confusion when dealing with a

mixture of “active low” and “active high” signals. The

term assert or assertion indicates that a signal is active

or true, independent of whether that level is repre-

sented by a high or low voltage. The term negate or

negation indicates that a signal is inactive or false.

CRYSTAL INPUT (XTAL2)

If a crystal is used, it is connected between XTAL1 and

this input, in which case a capacitor of approximately 15

to 33pF should be connected from this pin to ground. If

an external CMOS-level clock is used, this pin must be

left open.

-RESET (RESET)

The XR68C92/192 can be reset by asserting the -

X TA L1

X TA L2

X1

3.6863M H z

C1

22pF

C2

33pF

Figure 1: Crystal Connection

Rev. P1.10

8

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