MG65PB22 Просмотр технического описания (PDF) - Oki Electric Industry

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MG65PB22

0.25µm Embedded DRAM/Customer Structured Arrays

Oki Electric Industry 

s MG63P/64P/65P s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

MG63P/64P/65P FAMILY LISTING

Series (MG6x)

B02

B04

B06

B08

B10

B12

B14

B16

B18

B20

B22

B24

B26

B28

B30

B32

B34

B36

B38

B40

B42

No. of

Pads

68

108

148

188

228

268

308

348

388

428

468

508

548

588

628

668

708

748

788

828

868

No. of

Rows

84

144

204

264

324

384

444

504

564

624

684

744

804

864

924

984

1,044

1,104

1,164

1,224

1,284

No. of

Columns

280

480

680

880

1,080

1,280

1,480

1,680

1,880

2,080

2,280

2,480

2,680

2,880

3,080

3,280

3,480

3,680

3,880

4,080

4,280

No. of Raw

Gates

23,520

69,120

138,720

232,320

349,920

491,520

657,120

846,720

1,060,320

1,297,920

1,559,920

1,845,120

2,154,720

2,488,320

2,845,920

3,227,520

3,633,120

4,062,720

4,516,320

4,993,920

5,495,520

MG63P 3LM

Usable Gates

20,933

57,370

106,814

167,270

234,446

309,658

387,701

474,163

572,573

648,960

732,974

848,755

969,624

1,094,861

1,223,746

1,355,558

1,489,579

1,625,088

1,761,365

1,897,690

2,033,342

MG64P 4LM

Usable Gates

22,344

65,664

131,784

218,381

311,429

412,877

519,125

635,040

763,430

882,586

982,498

1,107,072

1,249,738

1,393,459

1,536,797

1,678,310

1,816,560

1,950,106

2,077,507

2,197,325

2,308,118

MG65P 5LM

Usable Gates

22,344

65,664

131,784

220,704

332,424

466,944

611,122

745,114

901,272

1,025,357

1,154,045

1,310,035

1,465,210

1,642,291

1,821,389

2,001,062

2,179,872

2,356,378

2,529,139

2,696,717

2,857,670

5 layer metal: MG65PBxx

4 layer metal: MG64PBxx

3 layer metal: MG63PBxx

ARRAY ARCHITECTURE

The primary components of a 0.25µm MG63P/64P/65P circuit include:

• I/O base cells

• 60µm pad pitch

• Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O)

• VDD and VSS pads dedicated to wafer probing

• Separate power bus for output buffers

• Separate power bus for internal core logic and input buffers

• Core base cells containing N-channel and P-channel pairs, arranged in column of gates

• Isolated gate structure for reduced input capacitance and increased routing flexibility

Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads

per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC)

and output drive transistors (VDDO and VSSO).

2

Oki Semiconductor

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