VSC7130RC Просмотр технического описания (PDF) - Vitesse Semiconductor

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VSC7130RC

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

Data Sheet

VSC7130

INPUT

DATA

VITESSE

SEMICONDUCTOR CORPORATION

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Figure 8: Retimer Block Diagram

Clock

Recovery

Unit

D

Q

CLKI CLKO

D

Q

CLKI

CLK

ADD/DROP

FIFO

To RTMRxC Register

UNDERx

OVERx

ADDx

DROPx

Retransmit

Flip-Flop

D

Q

CLK

OUTPUT

DATA

1.0625GHz Internal Baud Rate Clock

The internally generated baud rate clock (nominally 1.0625GHz) is used by the Retimer for several func-

tions. First, it provides the timing reference for the CRU. Second, it clocks data out of the FIFO. Third, it

retimes the retransmitted output data. The quality of the baud rate clock will impact the jitter tolerance of the

Clock Recovery Unit and the jitter generation of the Retransmitter Flip-Flop. The signal quality of the internally

generated baud rate clock is directly related to jitter on REFI and power supply noise. The user is encouraged to

minimize both REFI jitter and power supply noise in order to maximize jitter tolerance at the input and mini-

mize jitter generation at the output.

In the Add/Drop FIFO, a phase detector monitors the phase difference between the recovered clock and the

internally generated baud rate clock to determine when to add or drop Fill Words. Fill Words can only be added/

dropped between packets following the rules delineated by the Fibre Channel Specifications mentioned previ-

ously.

The retimer has two outputs indicating whether it is adding (ADDx) or dropping (DROPx) ordered sets

from the serial stream in order to perform rate matching between the incoming serial data and the local refer-

ence clock. The retimer also has an output (OVERx) indicating that an overrun condition has occurred when an

order set which needed to be dropped was not able to be dropped. Similarly, underrun errors are reported when

a Fill Word which needed to be added was not able to be added.

Please refer to the VSC7130 User’s Manual for more information regarding retimer operation and associ-

ated register controls.

Signal Detection

Associated with each CDR is a Signal Detect Unit (SDU) which is used to determine if a valid Fibre Chan-

nel signal is present at the CDR. Each SDU employs three independent checks to qualify the signal as valid:

K28.5- primitive detection, Run-Length-Limit (RLL) error detection and K28.5- density checking. In addition,

when the RX1 input pair is selected for input (instead of RX0), SDU1 also uses the Analog Signal Detect

(ASD) circuit associated with the RX1 input pair as an additional signal detect qualification.

Signal Detect assertions and deassertions are triggered by different conditions observed by the VSC7130 on

the incoming serial data signal. Signal Detect assertions are triggered only when two consecutive valid Fibre

G52297-0, Rev 4.0

04/02/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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