VSC7130RC Просмотр технического описания (PDF) - Vitesse Semiconductor

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VSC7130RC

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Data Sheet

VSC7130

Channel primitives containing K28.5- characters are received. Once Signal Detect is asserted, there are several

conditions which can result in the deassertion of Signal Detect: (1) An RLL error (a violation of 8B/10B coding

rules in which there are more than five consecutive zeros or ones in the data stream), (2) no K28.5- character

seen for one density window time (defaults to apx. 77 microseconds, but can be modified using the Two-Wire

Interface to write to the KWINDx-25h/2Dh register), or (3) an invalid signal level detected by the Analog Sig-

nal Detect circuit (only applies to SDU1 when the RX1 input is selected).

The Analog Signal Detect circuit is used to ensure that the signal amplitude presented to the RX1 input pair

is high enough to be considered valid. Analog transition detection is performed on the input to verify that the

signal swings are of adequate amplitude. The RX1+/- input buffer contains a differential voltage comparator

which has adjustable thresholds set by the external RXBIAS pin (see Figure 9). If the Two-Wire Interface is

being used, the Analog Signal Detect check for SDU1 can also be disabled by setting the ASDDIS1 register bit

(SDU1C-29h, bit).

Figure 9 shows an approximation to the Analog Signal Detect thresholds which can be obtained with bias-

ing resistors or another voltage reference source to the RXBIAS pin.

Figure 9: VSC7130 RXBIAS Equations and Graph

3.3V

R1

RXBIAS

R2

VSC7130

RXBIAS

Pin 46

R1 x R2

R1 + R2

<~

1kΩ

R1 <_ 3.3V - VRXBIAS

150uA

R2 <_

VRXBIAS

50uA

600

500

400

300

200

100

0.00

0.20

0.40

0.60

V RX BI AS /V D D

0.80

1.00

1. From the graph find the optimal SDET trip threshold for your system. It is recommended that

the rising edge of the graph be used unless pulling RXBIAS to ground via a 1kΩ resistor.

2. From the SDET threshold, determine the voltage level for RXBIAS from VRXBIAS/VDD. In

most systems, VDD is assumed to be 3.3V and VRXBIAS is the voltage seen at the RXBIAS pin.

3. Use the equations to determine the resistance values for R1 and R2. The use of 1% resistors for

R1 and R2 is recommended. Other regulated voltage sources may be used as long as the

minimal current is provided.

Page 10

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52297-0, Rev 4.0

04/02/01

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