VSC7130RC(2000) Просмотр технического описания (PDF) - Vitesse Semiconductor

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VSC7130RC
(Rev.:2000)

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7130

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Clock and Data Recovery (CDR)

Two Clock and Data Recovery Units (CDR) are included in the VSC7130 in order to improve signal quality

of serial data by amplification and jitter attenuation. The previous figure shows a block diagram of each with its

corresponding Signal Detect Unit (SDU). Each CDR may be configured as either a repeater or a retimer using

the MODE0, MODE1 and T/R pins or via the Two-Wire Interface by programming the MODEDIS, T/RDIS

and ITRx register bits.

Table 2: CDRx Repeater/Retimer Configuration

MODE1 pin

MODE0 pin

T/R pin

CDR1

CDR0

0

0

0

1

Repeater (SELRT1=1)

Repeater (SELRT1=1)

Repeater (SELRT0=1)

reTimer (SELRT0=0)

0

1

0

Repeater (SELRT1=1)

Repeater (SELRT0=1)

1

Repeater (SELRT1=1)

reTimer (SELRT0=0)

1

0

0

Repeater (SELRT1=1)

Repeater (SELRT0=1)

1

Repeater (SELRT1=1)

Repeater (SELRT0=1)

1

1

0

1

reTimer (SELRT1=0)

reTimer (SELRT1=0)

Repeater (SELRT0=1)

reTimer (SELRT0=0)

The SELRTx signal determines whether the repeater or retimer output is selected, as shown in Figure 6.

The MODEDIS register bit (CHIPCA-7) and the T/RDIS register bit (CHIPCA-4) can be used to disable the

pin controls defined in above table for selecting repeater or retimer mode for each CDR unit. For CDR0, if the

MODEDIS and T/RDIS bits are both set, the ITR0 register bit (CDR0C-4) will control the repeater/retimer

selection. For CDR1, only the MODEDIS register bit needs to be set in order to use ITR1 (CDR1C-4) to control

the repeater/retimer selection. A HIGH in ITRx selects repeater mode, and a LOW selects retimer mode.

Four sources of serial output data are selected by the BYPx signals: Serial Input (Bypass Mode), Ordered

Set Generators (either A or B as selected by OSGxSEL, bit 5 of the CDRxC register), the output of the Repeater

or the output of the Retimer.

Normally, the SI input passes through MUX1 to the input of CDR0 whose output is transmitted on TX+/- if

TXDIS is LOW. If TXDIS is HIGH, TX+ will be HIGH and TX- will be LOW. Similarly, the RX input nor-

mally passes through MUX2, CDR1 and MUX3 to the SO output.

The retimer has two outputs indicating whether it is adding (ADDx) or dropping (DROPx) ordered sets

from the serial stream in order to perform rate matching between the incoming serial data and the local refer-

ence clock. The retimer also has an output (OVERx) indicating that an overrun condition has occurred when an

order set which needed to be dropped was not able to be dropped. Similarly, underrun errors are reported when

a Fill Word which needed to be added was not able to be added.

Retimer Operation

NOTE: Retimer operation is only used for Fibre Channel data at 1.0625 Gb/s. Do not use Retimer mode

unless the incoming data is Fibre Channel or follows the Ordered Set structure defined by Fibre Channel. Fail-

ure to do so will result in data corruption.

When CDRx is configured as a Retimer, recovered data is resynchronized to an internally generated baud

rate clock derived from the REFI. This prevents jitter at the inputs from transferring to the outputs. However,

G52297-0, Rev. 2.3

1/17/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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