VSC7130(2000) Просмотр технического описания (PDF) - Vitesse Semiconductor
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VSC7130 Datasheet PDF : 22 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Dual Repeater/Retimer
for Fibre Channel and Gigabit Ethernet
Advance Product Information
VSC7130
AC Characteristics (Over Recommended Operating Conditions).
Figure 6: AC Timing Diagrams
RX0+/-
RX1+/-
SI1+/-
TX+/-
SO+/-
TP
TP
80%
20%
TS
TS
REFI
TT
TH
TT
TL
T
Table 6: AC Characteristics (Over recommended operating conditions).
VIH(MIN)
VIL(MAX)
Parameters
TP
TS
TJ(RPTR)
Description
Latency from any Serial Input to
any Serial Output
Differential Output Rise/Fall time
Total data output jitter
[Retimer Mode]
TDJ(RPTR)
Serial data output deterministic
jitter (p-p) [Retimer Mode]
TJ(RTMR)
Total data output jitter
[Retimer Mode]
TDJ(RTMR)
Serial data output deterministic
jitter (p-p) [Retimer Mode]
TJTOL
TT
F
FO
DC
TH , TL
Jitter Tolerance at RX0/RX1/SI
REFI input rise/fall times
REFI Frequency
Frequency Offset between
incoming data and REFI.
REFI Duty Cycle
REFI Input HIGH/LOW time
Min. Max. Units
Conditions
0.25 7.0
ns No Retimer in path
—
300
ps Between 20% and 80%
Jitter Generation at TX/SO when
—
192
ps driven by the CRU in Repeater Mode.
IEEE 802.3z Clause 38.68
Jitter Generation at TX/SO when
—
80
ps driven by the CRU in Repeater Mode.
IEEE 802.3z Clause 38.68
Jitter Generation at TX/SO when
—
192
ps driven by the CRU in Retimer Mode.
IEEE 802.3z Clause 38.68
Jitter Generation at TX/SO when
—
80
ps driven by the CRU in Retimer Mode.
IEEE 802.3z Clause 38.68
0.24 —
UI
Minimum Eye Opening for proper
operation as defined in MJS 8.0.
—
1.5
ns Between VIL(MAX) and VIH(MIN)
105
52.5
126
63
MHz
HALF/FULL is LOW
HALF/FULL is HIGH
-200 +200 ppm
30
70
% Measured at 1.5V
1.5
—
ns
From VIH(MIN) to VIH(MIN) or
VIL(MAX) to VIL(MAX)
Page 14
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52297-0, Rev. 2.3
1/17/00
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